Static Timing Analysis

Project : SAR_SPIM_USB08
Build Time : 02/14/15 11:19:28
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_0_theACLK(fixed-function) ADC_SAR_0_theACLK(fixed-function) 1.833 MHz 1.833 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 33.000 MHz 33.000 MHz N/A
ADC_SAR_0_theACLK CyMASTER_CLK 1.833 MHz 1.833 MHz N/A
CyBUS_CLK CyMASTER_CLK 33.000 MHz 33.000 MHz N/A
CyPLL_OUT CyPLL_OUT 33.000 MHz 33.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A