Static Timing Analysis

Project : USB_UARTtest
Build Time : 07/14/19 07:17:49
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 48.000 MHz 48.000 MHz N/A
Clock_1 CyMASTER_CLK 200.000  Hz 200.000  Hz 141.603 MHz
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 5e+006ns(200  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_15/q Net_5/main_0 141.603 MHz 7.062 4999992.938
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,4) 1 Net_15 Net_15/clock_0 Net_15/q 1.250
Route 1 Net_15 Net_15/q Net_5/main_0 2.302
macrocell4 U(0,4) 1 Net_5 SETUP 3.510
Clock Skew 0.000
\Debouncer_1:DEBOUNCER[0]:d_sync_1\/q Net_15/main_1 141.723 MHz 7.056 4999992.944
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_1\ \Debouncer_1:DEBOUNCER[0]:d_sync_1\/clock_0 \Debouncer_1:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \Debouncer_1:DEBOUNCER[0]:d_sync_1\ \Debouncer_1:DEBOUNCER[0]:d_sync_1\/q Net_15/main_1 2.296
macrocell3 U(0,4) 1 Net_15 SETUP 3.510
Clock Skew 0.000
\Debouncer_1:DEBOUNCER[0]:d_sync_0\/q \Debouncer_1:DEBOUNCER[0]:d_sync_1\/main_0 141.764 MHz 7.054 4999992.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q \Debouncer_1:DEBOUNCER[0]:d_sync_1\/main_0 2.294
macrocell2 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_1\ SETUP 3.510
Clock Skew 0.000
\Debouncer_1:DEBOUNCER[0]:d_sync_0\/q Net_15/main_0 141.764 MHz 7.054 4999992.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q Net_15/main_0 2.294
macrocell3 U(0,4) 1 Net_15 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\Debouncer_1:DEBOUNCER[0]:d_sync_0\/q \Debouncer_1:DEBOUNCER[0]:d_sync_1\/main_0 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q \Debouncer_1:DEBOUNCER[0]:d_sync_1\/main_0 2.294
macrocell2 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_1\ HOLD 0.000
Clock Skew 0.000
\Debouncer_1:DEBOUNCER[0]:d_sync_0\/q Net_15/main_0 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/clock_0 \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q 1.250
Route 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ \Debouncer_1:DEBOUNCER[0]:d_sync_0\/q Net_15/main_0 2.294
macrocell3 U(0,4) 1 Net_15 HOLD 0.000
Clock Skew 0.000
\Debouncer_1:DEBOUNCER[0]:d_sync_1\/q Net_15/main_1 3.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_1\ \Debouncer_1:DEBOUNCER[0]:d_sync_1\/clock_0 \Debouncer_1:DEBOUNCER[0]:d_sync_1\/q 1.250
Route 1 \Debouncer_1:DEBOUNCER[0]:d_sync_1\ \Debouncer_1:DEBOUNCER[0]:d_sync_1\/q Net_15/main_1 2.296
macrocell3 U(0,4) 1 Net_15 HOLD 0.000
Clock Skew 0.000
Net_15/q Net_5/main_0 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,4) 1 Net_15 Net_15/clock_0 Net_15/q 1.250
Route 1 Net_15 Net_15/q Net_5/main_0 2.302
macrocell4 U(0,4) 1 Net_5 HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_1
Source Destination Delay (ns)
Pin_input(0)_PAD \Debouncer_1:DEBOUNCER[0]:d_sync_0\/main_0 16.738
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_input(0)_PAD Pin_input(0)_PAD Pin_input(0)/pad_in 0.000
iocell3 P2[2] 1 Pin_input(0) Pin_input(0)/pad_in Pin_input(0)/fb 7.523
Route 1 Net_3 Pin_input(0)/fb \Debouncer_1:DEBOUNCER[0]:d_sync_0\/main_0 5.705
macrocell1 U(0,4) 1 \Debouncer_1:DEBOUNCER[0]:d_sync_0\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_5/q Pin_LED(0)_PAD:out 23.508
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,4) 1 Net_5 Net_5/clock_0 Net_5/q 1.250
Route 1 Net_5 Net_5/q Pin_LED(0)/pin_input 6.367
iocell4 P2[1] 1 Pin_LED(0) Pin_LED(0)/pin_input Pin_LED(0)/pad_out 15.891
Route 1 Pin_LED(0)_PAD Pin_LED(0)/pad_out Pin_LED(0)_PAD:out 0.000
Clock Clock path delay 0.000