Static Timing Analysis

Project : Data Acquisition
Build Time : 04/16/18 15:45:24
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk ADC_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ClockBlock/aclk_glb_ff_0 ClockBlock/aclk_glb_ff_0 UNKNOWN UNKNOWN N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
adc_clk CyMASTER_CLK 2.000 MHz 2.000 MHz N/A
dac_clk CyMASTER_CLK 1.000 MHz 1.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC:DSM\/dec_clock \ADC:DSM\/dec_clock UNKNOWN UNKNOWN N/A
dac_clk(routed) dac_clk(routed) 1.000 MHz 1.000 MHz N/A