Static Timing Analysis

Project : Design01
Build Time : 05/18/17 11:22:40
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk ADC_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ADC_theACLK(fixed-function) ADC_theACLK(fixed-function) 3.000 MHz 3.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 97.305 MHz
Clock_500Hz CyMASTER_CLK 12.000 MHz 12.000 MHz 88.771 MHz
SPI_IntClock CyMASTER_CLK 8.000 MHz 8.000 MHz 49.963 MHz
ADC_theACLK CyMASTER_CLK 3.000 MHz 3.000 MHz N/A
Clock_1GHz CyMASTER_CLK 1.000 MHz 1.000 MHz 89.039 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC:DSM\/dec_clock \ADC:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_2 89.039 MHz 11.231 988.769
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_Backlight:PWMUDB:tc_i\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Backlight:PWMUDB:status_2\/main_1 2.773
macrocell2 U(2,4) 1 \PWM_Backlight:PWMUDB:status_2\ \PWM_Backlight:PWMUDB:status_2\/main_1 \PWM_Backlight:PWMUDB:status_2\/q 3.350
Route 1 \PWM_Backlight:PWMUDB:status_2\ \PWM_Backlight:PWMUDB:status_2\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(2,4) 1 \PWM_Backlight:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 89.847 MHz 11.130 988.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.780
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_2 96.777 MHz 10.333 989.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/clock_0 \PWM_Backlight:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:status_2\/main_0 2.915
macrocell2 U(2,4) 1 \PWM_Backlight:PWMUDB:status_2\ \PWM_Backlight:PWMUDB:status_2\/main_0 \PWM_Backlight:PWMUDB:status_2\/q 3.350
Route 1 \PWM_Backlight:PWMUDB:status_2\ \PWM_Backlight:PWMUDB:status_2\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(2,4) 1 \PWM_Backlight:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 97.752 MHz 10.230 989.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/clock_0 \PWM_Backlight:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.920
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:status_0\/main_1 111.744 MHz 8.949 991.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_Backlight:PWMUDB:cmp1_less\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:status_0\/main_1 2.929
macrocell12 U(2,4) 1 \PWM_Backlight:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_246/main_1 111.757 MHz 8.948 991.052
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_Backlight:PWMUDB:cmp1_less\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_246/main_1 2.928
macrocell13 U(3,4) 1 Net_246 SETUP 3.510
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:prevCompare1\/main_0 111.970 MHz 8.931 991.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_Backlight:PWMUDB:cmp1_less\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:prevCompare1\/main_0 2.911
macrocell11 U(2,4) 1 \PWM_Backlight:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_Backlight:PWMUDB:runmode_enable\/q Net_246/main_0 130.480 MHz 7.664 992.336
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/clock_0 \PWM_Backlight:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/q Net_246/main_0 2.904
macrocell13 U(3,4) 1 Net_246 SETUP 3.510
Clock Skew 0.000
\PWM_Backlight:PWMUDB:prevCompare1\/q \PWM_Backlight:PWMUDB:status_0\/main_0 141.904 MHz 7.047 992.953
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,4) 1 \PWM_Backlight:PWMUDB:prevCompare1\ \PWM_Backlight:PWMUDB:prevCompare1\/clock_0 \PWM_Backlight:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:prevCompare1\ \PWM_Backlight:PWMUDB:prevCompare1\/q \PWM_Backlight:PWMUDB:status_0\/main_0 2.287
macrocell12 U(2,4) 1 \PWM_Backlight:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_Backlight:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Backlight:PWMUDB:runmode_enable\/main_0 142.066 MHz 7.039 992.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \PWM_Backlight:PWMUDB:genblk1:ctrlreg\ \PWM_Backlight:PWMUDB:genblk1:ctrlreg\/clock \PWM_Backlight:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM_Backlight:PWMUDB:control_7\ \PWM_Backlight:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Backlight:PWMUDB:runmode_enable\/main_0 2.319
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_2 88.771 MHz 11.265 72.068
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_MOSFET:PWMUDB:tc_i\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_MOSFET:PWMUDB:status_2\/main_1 2.812
macrocell8 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_2\ \PWM_MOSFET:PWMUDB:status_2\/main_1 \PWM_MOSFET:PWMUDB:status_2\/q 3.350
Route 1 \PWM_MOSFET:PWMUDB:status_2\ \PWM_MOSFET:PWMUDB:status_2\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell4 U(0,4) 1 \PWM_MOSFET:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 89.799 MHz 11.136 72.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.786
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:runmode_enable\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_2 95.621 MHz 10.458 72.875
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/clock_0 \PWM_MOSFET:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/q \PWM_MOSFET:PWMUDB:status_2\/main_0 3.045
macrocell8 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_2\ \PWM_MOSFET:PWMUDB:status_2\/main_0 \PWM_MOSFET:PWMUDB:status_2\/q 3.350
Route 1 \PWM_MOSFET:PWMUDB:status_2\ \PWM_MOSFET:PWMUDB:status_2\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell4 U(0,4) 1 \PWM_MOSFET:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:runmode_enable\/q \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 96.311 MHz 10.383 72.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/clock_0 \PWM_MOSFET:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/q \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.073
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1159/main_1 115.768 MHz 8.638 74.695
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_MOSFET:PWMUDB:cmp1_less\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1159/main_1 2.618
macrocell31 U(0,4) 1 Net_1159 SETUP 3.510
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:prevCompare1\/main_0 115.888 MHz 8.629 74.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_MOSFET:PWMUDB:cmp1_less\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:prevCompare1\/main_0 2.609
macrocell26 U(0,4) 1 \PWM_MOSFET:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:status_0\/main_1 115.888 MHz 8.629 74.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_MOSFET:PWMUDB:cmp1_less\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:status_0\/main_1 2.609
macrocell28 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1159/main_0 128.123 MHz 7.805 75.528
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/clock_0 \PWM_MOSFET:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1159/main_0 3.045
macrocell31 U(0,4) 1 Net_1159 SETUP 3.510
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1182/main_0 128.123 MHz 7.805 75.528
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/clock_0 \PWM_MOSFET:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1182/main_0 3.045
macrocell32 U(0,4) 1 Net_1182 SETUP 3.510
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:prevCompare1\/q \PWM_MOSFET:PWMUDB:status_0\/main_0 141.523 MHz 7.066 76.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,4) 1 \PWM_MOSFET:PWMUDB:prevCompare1\ \PWM_MOSFET:PWMUDB:prevCompare1\/clock_0 \PWM_MOSFET:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:prevCompare1\ \PWM_MOSFET:PWMUDB:prevCompare1\/q \PWM_MOSFET:PWMUDB:status_0\/main_0 2.306
macrocell28 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
MISO(0)/fb \SPI:BSPIM:sR8:Dp:u0\/route_si 97.305 MHz 10.277 31.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P15[5] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.092
Route 1 Net_45 MISO(0)/fb \SPI:BSPIM:sR8:Dp:u0\/route_si 4.685
datapathcell2 U(1,3) 1 \SPI:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Skew 0.000
Path Delay Requirement : 125ns(8 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPI:BSPIM:state_1\/q \SPI:BSPIM:mosi_pre_reg\/main_0 49.963 MHz 20.015 104.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,3) 1 \SPI:BSPIM:state_1\ \SPI:BSPIM:state_1\/clock_0 \SPI:BSPIM:state_1\/q 1.250
Route 1 \SPI:BSPIM:state_1\ \SPI:BSPIM:state_1\/q \SPI:BSPIM:mosi_pre_reg_split\/main_1 9.618
macrocell1 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/main_1 \SPI:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/q \SPI:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:state_1\/q \SPI:BSPIM:mosi_pre_reg\/main_1 49.993 MHz 20.003 104.997
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,3) 1 \SPI:BSPIM:state_1\ \SPI:BSPIM:state_1\/clock_0 \SPI:BSPIM:state_1\/q 1.250
Route 1 \SPI:BSPIM:state_1\ \SPI:BSPIM:state_1\/q \SPI:BSPIM:mosi_pre_reg_split_1\/main_1 9.599
macrocell30 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/main_1 \SPI:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/q \SPI:BSPIM:mosi_pre_reg\/main_1 2.294
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:state_2\/q \SPI:BSPIM:mosi_pre_reg\/main_1 51.135 MHz 19.556 105.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,3) 1 \SPI:BSPIM:state_2\ \SPI:BSPIM:state_2\/clock_0 \SPI:BSPIM:state_2\/q 1.250
Route 1 \SPI:BSPIM:state_2\ \SPI:BSPIM:state_2\/q \SPI:BSPIM:mosi_pre_reg_split_1\/main_0 9.152
macrocell30 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/main_0 \SPI:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/q \SPI:BSPIM:mosi_pre_reg\/main_1 2.294
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:sR8:Dp:u0\/so_comb \SPI:BSPIM:mosi_pre_reg\/main_1 53.277 MHz 18.770 106.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \SPI:BSPIM:sR8:Dp:u0\ \SPI:BSPIM:sR8:Dp:u0\/clock \SPI:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \SPI:BSPIM:mosi_from_dp\ \SPI:BSPIM:sR8:Dp:u0\/so_comb \SPI:BSPIM:mosi_pre_reg_split_1\/main_3 4.256
macrocell30 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/main_3 \SPI:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/q \SPI:BSPIM:mosi_pre_reg\/main_1 2.294
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:state_2\/q \SPI:BSPIM:mosi_pre_reg\/main_0 53.302 MHz 18.761 106.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,3) 1 \SPI:BSPIM:state_2\ \SPI:BSPIM:state_2\/clock_0 \SPI:BSPIM:state_2\/q 1.250
Route 1 \SPI:BSPIM:state_2\ \SPI:BSPIM:state_2\/q \SPI:BSPIM:mosi_pre_reg_split\/main_0 8.364
macrocell1 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/main_0 \SPI:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/q \SPI:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:state_0\/q \SPI:BSPIM:mosi_pre_reg\/main_1 53.507 MHz 18.689 106.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,3) 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/clock_0 \SPI:BSPIM:state_0\/q 1.250
Route 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/q \SPI:BSPIM:mosi_pre_reg_split_1\/main_2 8.285
macrocell30 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/main_2 \SPI:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/q \SPI:BSPIM:mosi_pre_reg\/main_1 2.294
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:state_0\/q \SPI:BSPIM:mosi_pre_reg\/main_0 53.917 MHz 18.547 106.453
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,3) 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/clock_0 \SPI:BSPIM:state_0\/q 1.250
Route 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/q \SPI:BSPIM:mosi_pre_reg_split\/main_2 8.150
macrocell1 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/main_2 \SPI:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/q \SPI:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:ld_ident\/q \SPI:BSPIM:mosi_pre_reg\/main_0 55.063 MHz 18.161 106.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,3) 1 \SPI:BSPIM:ld_ident\ \SPI:BSPIM:ld_ident\/clock_0 \SPI:BSPIM:ld_ident\/q 1.250
Route 1 \SPI:BSPIM:ld_ident\ \SPI:BSPIM:ld_ident\/q \SPI:BSPIM:mosi_pre_reg_split\/main_10 7.764
macrocell1 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/main_10 \SPI:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split\ \SPI:BSPIM:mosi_pre_reg_split\/q \SPI:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPI:BSPIM:RxStsReg\/status_6 55.078 MHz 18.156 106.844
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \SPI:BSPIM:sR8:Dp:u0\ \SPI:BSPIM:sR8:Dp:u0\/clock \SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.580
Route 1 \SPI:BSPIM:rx_status_4\ \SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPI:BSPIM:rx_status_6\/main_5 7.833
macrocell7 U(2,4) 1 \SPI:BSPIM:rx_status_6\ \SPI:BSPIM:rx_status_6\/main_5 \SPI:BSPIM:rx_status_6\/q 3.350
Route 1 \SPI:BSPIM:rx_status_6\ \SPI:BSPIM:rx_status_6\/q \SPI:BSPIM:RxStsReg\/status_6 2.893
statusicell3 U(2,3) 1 \SPI:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPI:BSPIM:ld_ident\/q \SPI:BSPIM:mosi_pre_reg\/main_1 55.106 MHz 18.147 106.853
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,3) 1 \SPI:BSPIM:ld_ident\ \SPI:BSPIM:ld_ident\/clock_0 \SPI:BSPIM:ld_ident\/q 1.250
Route 1 \SPI:BSPIM:ld_ident\ \SPI:BSPIM:ld_ident\/q \SPI:BSPIM:mosi_pre_reg_split_1\/main_9 7.743
macrocell30 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/main_9 \SPI:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPI:BSPIM:mosi_pre_reg_split_1\ \SPI:BSPIM:mosi_pre_reg_split_1\/q \SPI:BSPIM:mosi_pre_reg\/main_1 2.294
macrocell20 U(1,3) 1 \SPI:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_Backlight:PWMUDB:status_0\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_0 1.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,4) 1 \PWM_Backlight:PWMUDB:status_0\ \PWM_Backlight:PWMUDB:status_0\/clock_0 \PWM_Backlight:PWMUDB:status_0\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:status_0\ \PWM_Backlight:PWMUDB:status_0\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_0 2.325
statusicell1 U(2,4) 1 \PWM_Backlight:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Backlight:PWMUDB:runmode_enable\/main_0 2.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \PWM_Backlight:PWMUDB:genblk1:ctrlreg\ \PWM_Backlight:PWMUDB:genblk1:ctrlreg\/clock \PWM_Backlight:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_Backlight:PWMUDB:control_7\ \PWM_Backlight:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_Backlight:PWMUDB:runmode_enable\/main_0 2.319
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:prevCompare1\/q \PWM_Backlight:PWMUDB:status_0\/main_0 3.537
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,4) 1 \PWM_Backlight:PWMUDB:prevCompare1\ \PWM_Backlight:PWMUDB:prevCompare1\/clock_0 \PWM_Backlight:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:prevCompare1\ \PWM_Backlight:PWMUDB:prevCompare1\/q \PWM_Backlight:PWMUDB:status_0\/main_0 2.287
macrocell12 U(2,4) 1 \PWM_Backlight:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:prevCompare1\/main_0 3.691
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_Backlight:PWMUDB:cmp1_less\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:prevCompare1\/main_0 2.911
macrocell11 U(2,4) 1 \PWM_Backlight:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_246/main_1 3.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_Backlight:PWMUDB:cmp1_less\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_246/main_1 2.928
macrocell13 U(3,4) 1 Net_246 HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:status_0\/main_1 3.709
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_Backlight:PWMUDB:cmp1_less\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_Backlight:PWMUDB:status_0\/main_1 2.929
macrocell12 U(2,4) 1 \PWM_Backlight:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:runmode_enable\/q Net_246/main_0 4.154
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/clock_0 \PWM_Backlight:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/q Net_246/main_0 2.904
macrocell13 U(3,4) 1 Net_246 HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/clock_0 \PWM_Backlight:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.920
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.590
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/clock \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.780
datapathcell1 U(2,4) 1 \PWM_Backlight:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_2 7.833
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,4) 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/clock_0 \PWM_Backlight:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_Backlight:PWMUDB:runmode_enable\ \PWM_Backlight:PWMUDB:runmode_enable\/q \PWM_Backlight:PWMUDB:status_2\/main_0 2.915
macrocell2 U(2,4) 1 \PWM_Backlight:PWMUDB:status_2\ \PWM_Backlight:PWMUDB:status_2\/main_0 \PWM_Backlight:PWMUDB:status_2\/q 3.350
Route 1 \PWM_Backlight:PWMUDB:status_2\ \PWM_Backlight:PWMUDB:status_2\/q \PWM_Backlight:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(2,4) 1 \PWM_Backlight:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\PWM_MOSFET:PWMUDB:status_1\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_1 1.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_1\ \PWM_MOSFET:PWMUDB:status_1\/clock_0 \PWM_MOSFET:PWMUDB:status_1\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:status_1\ \PWM_MOSFET:PWMUDB:status_1\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_1 2.321
statusicell4 U(0,4) 1 \PWM_MOSFET:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:status_0\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_0\ \PWM_MOSFET:PWMUDB:status_0\/clock_0 \PWM_MOSFET:PWMUDB:status_0\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:status_0\ \PWM_MOSFET:PWMUDB:status_0\/q \PWM_MOSFET:PWMUDB:genblk8:stsreg\/status_0 2.323
statusicell4 U(0,4) 1 \PWM_MOSFET:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_MOSFET:PWMUDB:runmode_enable\/main_0 2.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,3) 1 \PWM_MOSFET:PWMUDB:genblk1:ctrlreg\ \PWM_MOSFET:PWMUDB:genblk1:ctrlreg\/clock \PWM_MOSFET:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_MOSFET:PWMUDB:control_7\ \PWM_MOSFET:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_MOSFET:PWMUDB:runmode_enable\/main_0 2.301
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:prevCompare1\/main_0 3.389
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_MOSFET:PWMUDB:cmp1_less\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:prevCompare1\/main_0 2.609
macrocell26 U(0,4) 1 \PWM_MOSFET:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:status_0\/main_1 3.389
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_MOSFET:PWMUDB:cmp1_less\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_MOSFET:PWMUDB:status_0\/main_1 2.609
macrocell28 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1159/main_1 3.398
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,4) 1 \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/clock \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_MOSFET:PWMUDB:cmp1_less\ \PWM_MOSFET:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1159/main_1 2.618
macrocell31 U(0,4) 1 Net_1159 HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:prevCompare2\/q \PWM_MOSFET:PWMUDB:status_1\/main_0 3.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,4) 1 \PWM_MOSFET:PWMUDB:prevCompare2\ \PWM_MOSFET:PWMUDB:prevCompare2\/clock_0 \PWM_MOSFET:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:prevCompare2\ \PWM_MOSFET:PWMUDB:prevCompare2\/q \PWM_MOSFET:PWMUDB:status_1\/main_0 2.292
macrocell29 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:prevCompare1\/q \PWM_MOSFET:PWMUDB:status_0\/main_0 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(0,4) 1 \PWM_MOSFET:PWMUDB:prevCompare1\ \PWM_MOSFET:PWMUDB:prevCompare1\/clock_0 \PWM_MOSFET:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:prevCompare1\ \PWM_MOSFET:PWMUDB:prevCompare1\/q \PWM_MOSFET:PWMUDB:status_0\/main_0 2.306
macrocell28 U(0,4) 1 \PWM_MOSFET:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1159/main_0 4.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/clock_0 \PWM_MOSFET:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1159/main_0 3.045
macrocell31 U(0,4) 1 Net_1159 HOLD 0.000
Clock Skew 0.000
\PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1182/main_0 4.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,3) 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/clock_0 \PWM_MOSFET:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_MOSFET:PWMUDB:runmode_enable\ \PWM_MOSFET:PWMUDB:runmode_enable\/q Net_1182/main_0 3.045
macrocell32 U(0,4) 1 Net_1182 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
MISO(0)/fb \SPI:BSPIM:sR8:Dp:u0\/route_si 6.777
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P15[5] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.092
Route 1 Net_45 MISO(0)/fb \SPI:BSPIM:sR8:Dp:u0\/route_si 4.685
datapathcell2 U(1,3) 1 \SPI:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPI:BSPIM:load_cond\/q \SPI:BSPIM:load_cond\/main_8 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ \SPI:BSPIM:load_cond\/clock_0 \SPI:BSPIM:load_cond\/q 1.250
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ \SPI:BSPIM:load_cond\/q \SPI:BSPIM:load_cond\/main_8 2.290
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:mosi_hs_reg\/q \SPI:BSPIM:mosi_hs_reg\/main_4 4.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,4) 1 \SPI:BSPIM:mosi_hs_reg\ \SPI:BSPIM:mosi_hs_reg\/clock_0 \SPI:BSPIM:mosi_hs_reg\/q 1.250
macrocell19 U(3,4) 1 \SPI:BSPIM:mosi_hs_reg\ \SPI:BSPIM:mosi_hs_reg\/q \SPI:BSPIM:mosi_hs_reg\/main_4 2.776
macrocell19 U(3,4) 1 \SPI:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:mosi_from_dp_reg\/q \SPI:BSPIM:mosi_hs_reg\/main_5 4.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,3) 1 \SPI:BSPIM:mosi_from_dp_reg\ \SPI:BSPIM:mosi_from_dp_reg\/clock_0 \SPI:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \SPI:BSPIM:mosi_from_dp_reg\ \SPI:BSPIM:mosi_from_dp_reg\/q \SPI:BSPIM:mosi_hs_reg\/main_5 2.923
macrocell19 U(3,4) 1 \SPI:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_cond\/main_6 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPI:BSPIM:count_1\ \SPI:BSPIM:BitCounter\/count_1 \SPI:BSPIM:load_cond\/main_6 3.728
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_cond\/main_7 4.407
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPI:BSPIM:count_0\ \SPI:BSPIM:BitCounter\/count_0 \SPI:BSPIM:load_cond\/main_7 3.787
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:load_cond\/main_3 4.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPI:BSPIM:count_4\ \SPI:BSPIM:BitCounter\/count_4 \SPI:BSPIM:load_cond\/main_3 3.791
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:load_cond\/main_5 4.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPI:BSPIM:count_2\ \SPI:BSPIM:BitCounter\/count_2 \SPI:BSPIM:load_cond\/main_5 3.820
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_cond\/main_4 4.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \SPI:BSPIM:BitCounter\ \SPI:BSPIM:BitCounter\/clock \SPI:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPI:BSPIM:count_3\ \SPI:BSPIM:BitCounter\/count_3 \SPI:BSPIM:load_cond\/main_4 3.820
macrocell21 U(1,4) 1 \SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPI:BSPIM:cnt_enable\/q \SPI:BSPIM:cnt_enable\/main_3 4.770
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(1,4) 1 \SPI:BSPIM:cnt_enable\ \SPI:BSPIM:cnt_enable\/clock_0 \SPI:BSPIM:cnt_enable\/q 1.250
macrocell24 U(1,4) 1 \SPI:BSPIM:cnt_enable\ \SPI:BSPIM:cnt_enable\/q \SPI:BSPIM:cnt_enable\/main_3 3.520
macrocell24 U(1,4) 1 \SPI:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
Net_44/q Net_44/main_0 5.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 Net_44 Net_44/clock_0 Net_44/q 1.250
macrocell15 U(3,4) 1 Net_44 Net_44/q Net_44/main_0 3.765
macrocell15 U(3,4) 1 Net_44 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1GHz
Source Destination Delay (ns)
Net_246/q Backlight(0)_PAD 23.081
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,4) 1 Net_246 Net_246/clock_0 Net_246/q 1.250
Route 1 Net_246 Net_246/q Backlight(0)/pin_input 6.336
iocell3 P0[7] 1 Backlight(0) Backlight(0)/pin_input Backlight(0)/pad_out 15.495
Route 1 Backlight(0)_PAD Backlight(0)/pad_out Backlight(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_500Hz
Source Destination Delay (ns)
Net_1159/q Battery(0)_PAD 23.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(0,4) 1 Net_1159 Net_1159/clock_0 Net_1159/q 1.250
Route 1 Net_1159 Net_1159/q Battery(0)/pin_input 6.359
iocell14 P2[0] 1 Battery(0) Battery(0)/pin_input Battery(0)/pad_out 15.667
Route 1 Battery(0)_PAD Battery(0)/pad_out Battery(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1182/q Solar_Panel(0)_PAD 22.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(0,4) 1 Net_1182 Net_1182/clock_0 Net_1182/q 1.250
Route 1 Net_1182 Net_1182/q Solar_Panel(0)/pin_input 5.497
iocell15 P2[1] 1 Solar_Panel(0) Solar_Panel(0)/pin_input Solar_Panel(0)/pad_out 15.891
Route 1 Solar_Panel(0)_PAD Solar_Panel(0)/pad_out Solar_Panel(0)_PAD 0.000
Clock Clock path delay 0.000
+ SPI_IntClock
Source Destination Delay (ns)
\SPI:BSPIM:state_0\/q MOSI(0)_PAD 33.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,3) 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/clock_0 \SPI:BSPIM:state_0\/q 1.250
Route 1 \SPI:BSPIM:state_0\ \SPI:BSPIM:state_0\/q Net_43/main_3 8.068
macrocell4 U(3,4) 1 Net_43 Net_43/main_3 Net_43/q 3.350
Route 1 Net_43 Net_43/q MOSI(0)/pin_input 5.433
iocell9 P0[0] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 15.251
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_136/q SS(0)_PAD 25.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(3,3) 1 Net_136 Net_136/clock_0 Net_136/q 1.250
Route 1 Net_136 Net_136/q SS(0)/pin_input 8.654
iocell4 P15[3] 1 SS(0) SS(0)/pin_input SS(0)/pad_out 15.486
Route 1 SS(0)_PAD SS(0)/pad_out SS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_44/q SCLK(0)_PAD 23.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,4) 1 Net_44 Net_44/clock_0 Net_44/q 1.250
Route 1 Net_44 Net_44/q SCLK(0)/pin_input 6.618
iocell8 P0[1] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 15.802
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000