Static Timing Analysis

Project : ceshi2
Build Time : 03/27/14 14:50:14
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_1_theACLK(fixed-function) ADC_SAR_1_theACLK(fixed-function) 6.000 MHz 6.000 MHz N/A
ADC_SAR_2_theACLK(fixed-function) ADC_SAR_2_theACLK(fixed-function) 6.000 MHz 6.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_SAR_1_theACLK CyMASTER_CLK 6.000 MHz 6.000 MHz N/A
ADC_SAR_2_theACLK CyMASTER_CLK 6.000 MHz 6.000 MHz N/A
WaveDAC8_2_DacClk CyMASTER_CLK 20.000 kHz 20.000 kHz N/A
WaveDAC8_1_DacClk CyMASTER_CLK 20.000 kHz 20.000 kHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
WaveDAC8_1_DacClk(routed) WaveDAC8_1_DacClk(routed) 20.000 kHz 20.000 kHz N/A
WaveDAC8_2_DacClk(routed) WaveDAC8_2_DacClk(routed) 20.000 kHz 20.000 kHz N/A