Static Timing Analysis

Project : Timer
Build Time : 04/18/12 15:59:13
Device : CY8C5588AXI-060ES1
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Setup
CyBUS_CLK clock_1 -3.104
CyBUS_CLK clock_3 -3.415
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
ClockBlock/dclk_0 Async 10.000 kHz 10.000 kHz N/A
ClockBlock/dclk_1 Async 10.000 kHz 10.000 kHz N/A
ClockBlock/dclk_2 Async 2.000 kHz 2.000 kHz N/A
ClockBlock/dclk_3 Async 2.000 kHz 2.000 kHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz 22.182 MHz Frequency
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
clock_1 Sync 10.000 kHz 10.000 kHz 22.336 MHz
clock_2 Sync 2.000 kHz 2.000 kHz 77.821 MHz
clock_3 Sync 10.000 kHz 10.000 kHz 22.182 MHz
clock_4 Sync 2.000 kHz 2.000 kHz 70.408 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 22.336 MHz 44.771 -3.104 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 24.119 MHz 41.461 0.206
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 24.121 MHz 41.457 0.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.004
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 25.486 MHz 39.237 2.430
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.094
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 26.212 MHz 38.151 3.516
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 26.214 MHz 38.147 3.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.004
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_2 27.808 MHz 35.961 5.706
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_2 6.098
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 11.520
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 27.811 MHz 35.957 5.710
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.094
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 11.520
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 28.677 MHz 34.871 6.796
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 28.680 MHz 34.867 6.800
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.004
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 22.182 MHz 45.082 -3.415 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 23.931 MHz 41.787 -0.120 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.303
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 23.939 MHz 41.772 -0.105 SETUP
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 25.418 MHz 39.342 2.325
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.168
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 25.990 MHz 38.477 3.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.303
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 26.000 MHz 38.462 3.205
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_2 27.722 MHz 36.072 5.595
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_2 6.178
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 11.520
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 27.730 MHz 36.062 5.605
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.168
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 11.520
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 28.412 MHz 35.197 6.470
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.303
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 28.424 MHz 35.182 6.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 30.088 MHz 33.236 99966.764
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 31.441 MHz 31.806 99968.194
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 32.921 MHz 30.376 99969.624
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 33.402 MHz 29.938 99970.062
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.688
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 33.416 MHz 29.926 99970.074
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/z0 \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0i \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 34.547 MHz 28.946 99971.054
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/clock \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 3.850
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 35.078 MHz 28.508 99971.492
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.688
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 35.093 MHz 28.496 99971.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0i \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 36.930 MHz 27.078 99972.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.688
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 36.947 MHz 27.066 99972.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u0\/f0_load 77.821 MHz 12.850 28.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u0\/f0_load 4.022
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ SETUP 1.930
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u1\/f0_load 77.827 MHz 12.849 28.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u1\/f0_load 4.021
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ SETUP 1.930
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u3\/f0_load 83.738 MHz 11.942 29.725
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u3\/f0_load 3.114
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ SETUP 1.930
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u2\/f0_load 84.904 MHz 11.778 29.889
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u2\/f0_load 2.950
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ SETUP 1.930
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 86.311 MHz 11.586 30.081
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 3.118
statusicell1 U(1,3) 1 \Timer_1:TimerUDB:nrstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:capture_last\/main_0 141.683 MHz 7.058 34.609
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capture_last\/main_0 2.298
macrocell6 U(0,3) 1 \Timer_1:TimerUDB:capture_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 100000ns(10 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer_2:TimerUDB:sT32:timerdp:u0\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 29.836 MHz 33.516 99966.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/clock \Timer_2:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/z0 \Timer_2:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0i \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 31.166 MHz 32.086 99967.914
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/clock \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 32.620 MHz 30.656 99969.344
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/clock \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u0\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 33.102 MHz 30.210 99969.790
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/clock \Timer_2:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/z0 \Timer_2:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0i \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.960
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u0\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 33.106 MHz 30.206 99969.794
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/clock \Timer_2:TimerUDB:sT32:timerdp:u0\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/z0 \Timer_2:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0i \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 34.216 MHz 29.226 99970.774
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/clock \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 3.850
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 34.746 MHz 28.780 99971.220
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/clock \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.960
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 34.751 MHz 28.776 99971.224
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/clock \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0i \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.430
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 36.563 MHz 27.350 99972.650
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/clock \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.960
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 5.090
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 36.568 MHz 27.346 99972.654
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/clock \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 2.320
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.960
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.310
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 5.090
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u0\/f0_load 70.408 MHz 14.203 27.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u0\/f0_load 5.373
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ SETUP 1.930
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u1\/f0_load 73.282 MHz 13.646 28.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u1\/f0_load 4.816
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ SETUP 1.930
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u3\/f0_load 83.822 MHz 11.930 29.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u3\/f0_load 3.100
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ SETUP 1.930
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u2\/f0_load 84.789 MHz 11.794 29.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u2\/f0_load 2.964
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ SETUP 1.930
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:nrstSts:stsreg\/status_1 86.393 MHz 11.575 30.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:nrstSts:stsreg\/status_1 3.105
statusicell2 U(2,2) 1 \Timer_2:TimerUDB:nrstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:capture_last\/main_0 141.643 MHz 7.060 34.607
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capture_last\/main_0 2.300
macrocell9 U(2,2) 1 \Timer_2:TimerUDB:capture_last\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 23.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.004
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 23.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 24.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.094
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_2 24.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_2 6.098
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 33.057
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.004
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 33.061
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 34.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.094
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 35.677
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.004
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 35.681
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 38.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P15[1] 1 Pin_Rst1(0) Pin_Rst1(0)/clock Pin_Rst1(0)/fb 18.343
Route 1 Net_12 Pin_Rst1(0)/fb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.008
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 23.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 23.677
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.303
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 24.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.168
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_2 24.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_2 6.178
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 33.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 33.387
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.303
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 34.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 6.168
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 35.992
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 36.007
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 5.303
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 38.612
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P12[4] 1 Pin_Rst2(0) Pin_Rst2(0)/clock Pin_Rst2(0)/fb 18.374
Route 1 Net_208 Pin_Rst2(0)/fb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 5.288
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_2 \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 9.710
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ \Timer_1:TimerUDB:sT32:timerdp:u0\/clock \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/ci \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ \Timer_1:TimerUDB:sT32:timerdp:u1\/clock \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/ci \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_1:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_0 6.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/clock \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_0 2.760
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_0 6.041
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/clock \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u2\/cs_addr_0 2.771
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 6.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/clock \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.676
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 6.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/clock \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_1:TimerUDB:per_zero\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.688
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_0 7.240
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ \Timer_1:TimerUDB:sT32:timerdp:u2\/clock \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 1.740
Route 1 \Timer_1:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_1:TimerUDB:sT32:timerdp:u2\/z0 \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0i \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ \Timer_1:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_1:TimerUDB:sT32:timerdp:u3\/cs_addr_0 2.760
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_236/q \Timer_1:TimerUDB:capture_last\/main_0 99961.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capture_last\/main_0 2.298
macrocell6 U(0,3) 1 \Timer_1:TimerUDB:capture_last\ HOLD 0.000
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 99966.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:nrstSts:stsreg\/status_1 3.118
statusicell1 U(1,3) 1 \Timer_1:TimerUDB:nrstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u2\/f0_load 99968.181
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u2\/f0_load 2.950
datapathcell3 U(0,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u3\/f0_load 99968.345
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u3\/f0_load 3.114
datapathcell4 U(1,3) 1 \Timer_1:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u1\/f0_load 99969.252
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u1\/f0_load 4.021
datapathcell2 U(0,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
Net_236/q \Timer_1:TimerUDB:sT32:timerdp:u0\/f0_load 99969.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,3) 1 Net_236 Net_236/clock_0 Net_236/q 1.250
Route 1 Net_236 Net_236/q \Timer_1:TimerUDB:capt_fifo_load\/main_2 2.298
macrocell5 U(0,3) 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/main_2 \Timer_1:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_1:TimerUDB:capt_fifo_load\ \Timer_1:TimerUDB:capt_fifo_load\/q \Timer_1:TimerUDB:sT32:timerdp:u0\/f0_load 4.022
datapathcell1 U(1,2) 1 \Timer_1:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/clock \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/clock \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/clock \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 3.210
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ \Timer_2:TimerUDB:sT32:timerdp:u0\/clock \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb 3.210
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u0\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/ci \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 2.620
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 5.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ \Timer_2:TimerUDB:sT32:timerdp:u1\/clock \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb 3.210
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u1\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/ci \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb 2.620
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/co_msb \Timer_2:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_0 6.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/clock \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_0 2.876
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_0 6.149
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/clock \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u2\/cs_addr_0 2.879
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 7.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/clock \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.956
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 7.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/clock \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 3.270
Route 1 \Timer_2:TimerUDB:per_zero\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.960
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_0 7.356
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ \Timer_2:TimerUDB:sT32:timerdp:u2\/clock \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 1.740
Route 1 \Timer_2:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer_2:TimerUDB:sT32:timerdp:u2\/z0 \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0i \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ \Timer_2:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer_2:TimerUDB:sT32:timerdp:u3\/cs_addr_0 2.876
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_248/q \Timer_2:TimerUDB:capture_last\/main_0 99961.883
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capture_last\/main_0 2.300
macrocell9 U(2,2) 1 \Timer_2:TimerUDB:capture_last\ HOLD 0.000
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:nrstSts:stsreg\/status_1 99966.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:nrstSts:stsreg\/status_1 3.105
statusicell2 U(2,2) 1 \Timer_2:TimerUDB:nrstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u2\/f0_load 99968.197
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u2\/f0_load 2.964
datapathcell7 U(3,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u3\/f0_load 99968.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u3\/f0_load 3.100
datapathcell8 U(2,2) 1 \Timer_2:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u1\/f0_load 99970.049
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u1\/f0_load 4.816
datapathcell6 U(3,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
Net_248/q \Timer_2:TimerUDB:sT32:timerdp:u0\/f0_load 99970.606
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(2,2) 1 Net_248 Net_248/clock_0 Net_248/q 1.250
Route 1 Net_248 Net_248/q \Timer_2:TimerUDB:capt_fifo_load\/main_0 2.300
macrocell8 U(2,2) 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/main_0 \Timer_2:TimerUDB:capt_fifo_load\/q 3.350
Route 1 \Timer_2:TimerUDB:capt_fifo_load\ \Timer_2:TimerUDB:capt_fifo_load\/q \Timer_2:TimerUDB:sT32:timerdp:u0\/f0_load 5.373
datapathcell5 U(2,3) 1 \Timer_2:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000