Static Timing Analysis

Project : P5Kit_PGA_and_USB
Build Time : 02/18/16 15:38:43
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_1_Ext_CP_Clk ADC_DelSig_1_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_Ext_CP_Clk(routed) ADC_DelSig_1_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ADC_DelSig_1_theACLK(fixed-function) ADC_DelSig_1_theACLK(fixed-function) 3.000 MHz 3.000 MHz N/A
ADC_SAR_1_theACLK(routed) ADC_SAR_1_theACLK(routed) 1.600 MHz 1.600 MHz N/A
ADC_SAR_2_theACLK(routed) ADC_SAR_2_theACLK(routed) 1.600 MHz 1.600 MHz N/A
CyILO CyILO 100.000 kHz 100.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 60.588 MHz
ADC_DelSig_1_theACLK CyMASTER_CLK 3.000 MHz 3.000 MHz N/A
ADC_SAR_2_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
ADC_SAR_1_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 59.361 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
\ADC_DelSig_1:DSM\/dec_clock \ADC_DelSig_1:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 60.588 MHz 16.505 25.162
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.448
macrocell6 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 84.338 MHz 11.857 29.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.338
macrocell23 U(0,1) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 85.237 MHz 11.732 29.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.213
macrocell22 U(0,1) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 85.237 MHz 11.732 29.935
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.213
macrocell25 U(0,1) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 90.909 MHz 11.000 30.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.481
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 90.909 MHz 11.000 30.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.481
macrocell24 U(0,0) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 91.183 MHz 10.967 30.700
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.448
macrocell16 U(0,0) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.361 MHz 16.846 13024.821
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.761
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 59.909 MHz 16.692 13024.975
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 4.483
macrocell5 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.779 MHz 16.453 13025.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.368
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.751 MHz 16.194 13025.473
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 3.109
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 63.841 MHz 15.664 13026.003
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,0) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 3.455
macrocell5 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.185 MHz 15.580 13026.087
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 3.371
macrocell5 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 64.800 MHz 15.432 13026.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 3.407
macrocell2 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.295
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 66.353 MHz 15.071 13026.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 2.862
macrocell5 U(0,0) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.249
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 69.478 MHz 14.393 13027.274
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,1) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 4.095
macrocell6 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 70.681 MHz 14.148 13027.519
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,1) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 3.850
macrocell6 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.448
macrocell16 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.481
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 7.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.481
macrocell24 U(0,0) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 8.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.213
macrocell22 U(0,1) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 8.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.213
macrocell25 U(0,1) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 8.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.338
macrocell23 U(0,1) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 13.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_78 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.448
macrocell6 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.261
statusicell2 U(1,0) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.798
macrocell10 U(1,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.798
macrocell11 U(1,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 3.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.812
macrocell13 U(0,1) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 3.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.571
macrocell17 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 3.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 2.571
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 3.196
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.576
macrocell17 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_5 3.196
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_5 2.576
macrocell19 U(0,0) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 3.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 2.582
macrocell16 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 3.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 2.582
macrocell18 U(0,0) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 30.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_73/main_0 3.194
macrocell1 U(1,0) 1 Net_73 Net_73/main_0 Net_73/q 3.350
Route 1 Net_73 Net_73/q Tx_1(0)/pin_input 5.431
iocell2 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000