\UART:BUART:tx_state_0\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
49.371 MHz |
20.255 |
13021.412 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell16 |
U(2,3) |
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/clock_0 |
\UART:BUART:tx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_0\ |
\UART:BUART:tx_state_0\/q |
\UART:BUART:counter_load_not\/main_1 |
5.799 |
macrocell2 |
U(2,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_1 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.666 |
datapathcell2 |
U(2,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_1\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
49.657 MHz |
20.138 |
13021.529 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell15 |
U(2,1) |
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/clock_0 |
\UART:BUART:tx_state_1\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_1\ |
\UART:BUART:tx_state_1\/q |
\UART:BUART:counter_load_not\/main_0 |
5.682 |
macrocell2 |
U(2,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_0 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.666 |
datapathcell2 |
U(2,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
53.186 MHz |
18.802 |
13022.865 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(2,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART:BUART:tx_bitclk_enable_pre\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:counter_load_not\/main_2 |
5.406 |
macrocell2 |
U(2,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_2 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.666 |
datapathcell2 |
U(2,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_state_2\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
55.081 MHz |
18.155 |
13023.512 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell17 |
U(2,3) |
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/clock_0 |
\UART:BUART:tx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_state_2\ |
\UART:BUART:tx_state_2\/q |
\UART:BUART:counter_load_not\/main_3 |
3.699 |
macrocell2 |
U(2,4) |
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/main_3 |
\UART:BUART:counter_load_not\/q |
3.350 |
Route |
|
1 |
\UART:BUART:counter_load_not\ |
\UART:BUART:counter_load_not\/q |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 |
3.666 |
datapathcell2 |
U(2,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
|
SETUP |
6.190 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:tx_ctrl_mark_last\/q |
\UART:BUART:sRX:RxBitCounter\/load |
59.242 MHz |
16.880 |
13024.787 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell19 |
U(3,3) |
1 |
\UART:BUART:tx_ctrl_mark_last\ |
\UART:BUART:tx_ctrl_mark_last\/clock_0 |
\UART:BUART:tx_ctrl_mark_last\/q |
1.250 |
Route |
|
1 |
\UART:BUART:tx_ctrl_mark_last\ |
\UART:BUART:tx_ctrl_mark_last\/q |
\UART:BUART:rx_counter_load\/main_0 |
4.609 |
macrocell5 |
U(3,2) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_0 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(3,2) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_2\/q |
\UART:BUART:sRX:RxBitCounter\/load |
62.873 MHz |
15.905 |
13025.762 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell23 |
U(3,2) |
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/clock_0 |
\UART:BUART:rx_state_2\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_2\ |
\UART:BUART:rx_state_2\/q |
\UART:BUART:rx_counter_load\/main_3 |
3.634 |
macrocell5 |
U(3,2) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_3 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(3,2) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_0\/q |
\UART:BUART:sRX:RxBitCounter\/load |
63.456 MHz |
15.759 |
13025.908 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell20 |
U(3,2) |
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/clock_0 |
\UART:BUART:rx_state_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_0\ |
\UART:BUART:rx_state_0\/q |
\UART:BUART:rx_counter_load\/main_1 |
3.488 |
macrocell5 |
U(3,2) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_1 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(3,2) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:rx_state_3\/q |
\UART:BUART:sRX:RxBitCounter\/load |
66.489 MHz |
15.040 |
13026.627 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell22 |
U(3,2) |
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/clock_0 |
\UART:BUART:rx_state_3\/q |
1.250 |
Route |
|
1 |
\UART:BUART:rx_state_3\ |
\UART:BUART:rx_state_3\/q |
\UART:BUART:rx_counter_load\/main_2 |
2.769 |
macrocell5 |
U(3,2) |
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/main_2 |
\UART:BUART:rx_counter_load\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_counter_load\ |
\UART:BUART:rx_counter_load\/q |
\UART:BUART:sRX:RxBitCounter\/load |
2.311 |
count7cell |
U(3,2) |
1 |
\UART:BUART:sRX:RxBitCounter\ |
|
SETUP |
5.360 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:pollcount_0\/q |
\UART:BUART:sRX:RxShifter:u0\/route_si |
67.240 MHz |
14.872 |
13026.795 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
macrocell27 |
U(3,0) |
1 |
\UART:BUART:pollcount_0\ |
\UART:BUART:pollcount_0\/clock_0 |
\UART:BUART:pollcount_0\/q |
1.250 |
Route |
|
1 |
\UART:BUART:pollcount_0\ |
\UART:BUART:pollcount_0\/q |
\UART:BUART:rx_postpoll\/main_2 |
3.132 |
macrocell6 |
U(3,1) |
1 |
\UART:BUART:rx_postpoll\ |
\UART:BUART:rx_postpoll\/main_2 |
\UART:BUART:rx_postpoll\/q |
3.350 |
Route |
|
1 |
\UART:BUART:rx_postpoll\ |
\UART:BUART:rx_postpoll\/q |
\UART:BUART:sRX:RxShifter:u0\/route_si |
3.670 |
datapathcell3 |
U(3,3) |
1 |
\UART:BUART:sRX:RxShifter:u0\ |
|
SETUP |
3.470 |
Clock |
|
|
|
|
Skew |
0.000 |
|
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:sTX:TxSts\/status_0 |
69.599 MHz |
14.368 |
13027.299 |
|
Type |
Location |
Fanout |
Instance/Net |
Source |
Dest |
Delay (ns) |
datapathcell2 |
U(2,2) |
1 |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
0.190 |
Route |
|
1 |
\UART:BUART:tx_bitclk_enable_pre\ |
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg |
\UART:BUART:tx_status_0\/main_2 |
8.003 |
macrocell3 |
U(2,3) |
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/main_2 |
\UART:BUART:tx_status_0\/q |
3.350 |
Route |
|
1 |
\UART:BUART:tx_status_0\ |
\UART:BUART:tx_status_0\/q |
\UART:BUART:sTX:TxSts\/status_0 |
2.325 |
statusicell1 |
U(2,3) |
1 |
\UART:BUART:sTX:TxSts\ |
|
SETUP |
0.500 |
Clock |
|
|
|
|
Skew |
0.000 |
|