Static Timing Analysis

Project : filesystem_1
Build Time : 01/10/19 14:33:23
Device : CY8C5267AXI-LP051
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 51.306 MHz
SPIM_IntClock CyMASTER_CLK 1.000 MHz 1.000 MHz 51.002 MHz
UART_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 49.371 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL CyXTAL 8.000 MHz 8.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 51.306 MHz 19.491 22.176
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 6.992
macrocell6 U(3,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 3.670
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 73.573 MHz 13.592 28.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 8.073
macrocell23 U(3,2) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 73.670 MHz 13.574 28.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 8.055
macrocell20 U(3,2) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 73.670 MHz 13.574 28.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 8.055
macrocell28 U(3,2) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 79.930 MHz 12.511 29.156
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 6.992
macrocell26 U(3,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 84.660 MHz 11.812 29.855
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 6.293
macrocell27 U(3,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 84.660 MHz 11.812 29.855
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 6.293
macrocell29 U(3,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1000ns(1 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:RxStsReg\/status_6 51.002 MHz 19.607 980.393
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:rx_status_6\/main_0 11.509
macrocell13 U(2,1) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_0 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.308
statusicell4 U(2,1) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 51.188 MHz 19.536 980.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 9.806
datapathcell4 U(3,4) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 8.480
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:TxStsReg\/status_3 51.459 MHz 19.433 980.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:dpcounter_one\/main_3 8.268
macrocell10 U(3,0) 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/main_3 \SPIM:BSPIM:dpcounter_one\/q 3.350
Route 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/q \SPIM:BSPIM:TxStsReg\/status_3 5.375
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:TxStsReg\/status_3 52.773 MHz 18.949 981.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:dpcounter_one\/main_0 7.784
macrocell10 U(3,0) 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/main_0 \SPIM:BSPIM:dpcounter_one\/q 3.350
Route 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/q \SPIM:BSPIM:TxStsReg\/status_3 5.375
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:TxStsReg\/status_3 53.479 MHz 18.699 981.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:dpcounter_one\/main_2 7.534
macrocell10 U(3,0) 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/main_2 \SPIM:BSPIM:dpcounter_one\/q 3.350
Route 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/q \SPIM:BSPIM:TxStsReg\/status_3 5.375
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:TxStsReg\/status_0 54.484 MHz 18.354 981.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:tx_status_0\/main_0 7.438
macrocell11 U(3,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_0 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 5.816
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:TxStsReg\/status_3 54.523 MHz 18.341 981.659
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:dpcounter_one\/main_1 7.176
macrocell10 U(3,0) 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/main_1 \SPIM:BSPIM:dpcounter_one\/q 3.350
Route 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/q \SPIM:BSPIM:TxStsReg\/status_3 5.375
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:TxStsReg\/status_0 54.822 MHz 18.241 981.759
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,4) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:tx_status_0\/main_2 7.325
macrocell11 U(3,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_2 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 5.816
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 56.702 MHz 17.636 982.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:dpcounter_one\/main_4 6.471
macrocell10 U(3,0) 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/main_4 \SPIM:BSPIM:dpcounter_one\/q 3.350
Route 1 \SPIM:BSPIM:dpcounter_one\ \SPIM:BSPIM:dpcounter_one\/q \SPIM:BSPIM:TxStsReg\/status_3 5.375
statusicell3 U(3,0) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_2\/main_3 56.905 MHz 17.573 982.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:state_2\/main_3 12.123
macrocell31 U(2,0) 1 \SPIM:BSPIM:state_2\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 49.371 MHz 20.255 13021.412
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,3) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 5.799
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.666
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 49.657 MHz 20.138 13021.529
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 5.682
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.666
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 53.186 MHz 18.802 13022.865
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 5.406
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.666
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.081 MHz 18.155 13023.512
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,3) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 3.699
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.666
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 59.242 MHz 16.880 13024.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,3) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 4.609
macrocell5 U(3,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 62.873 MHz 15.905 13025.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,2) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 3.634
macrocell5 U(3,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 63.456 MHz 15.759 13025.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,2) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 3.488
macrocell5 U(3,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 66.489 MHz 15.040 13026.627
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,2) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 2.769
macrocell5 U(3,2) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 67.240 MHz 14.872 13026.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 3.132
macrocell6 U(3,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 3.670
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:TxSts\/status_0 69.599 MHz 14.368 13027.299
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_status_0\/main_2 8.003
macrocell3 U(2,3) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_2 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.325
statusicell1 U(2,3) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 8.302
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 6.293
macrocell27 U(3,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 8.302
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 6.293
macrocell29 U(3,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 9.001
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 6.992
macrocell26 U(3,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 10.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 8.055
macrocell20 U(3,2) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 10.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 8.055
macrocell28 U(3,2) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 10.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 8.073
macrocell23 U(3,2) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 16.021
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_120 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 6.992
macrocell6 U(3,1) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 3.670
datapathcell3 U(3,3) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 3.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.610
macrocell30 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:mosi_pre_reg\/main_5 3.241
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:mosi_pre_reg\/main_5 2.621
macrocell36 U(2,4) 1 \SPIM:BSPIM:mosi_pre_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 3.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.634
macrocell30 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:mosi_pre_reg\/main_7 3.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:mosi_pre_reg\/main_7 2.647
macrocell36 U(2,4) 1 \SPIM:BSPIM:mosi_pre_reg\ HOLD 0.000
Clock Skew 0.000
Net_155/q Net_155/main_3 3.471
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(3,0) 1 Net_155 Net_155/clock_0 Net_155/q 1.250
macrocell34 U(3,0) 1 Net_155 Net_155/q Net_155/main_3 2.221
macrocell34 U(3,0) 1 Net_155 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_3 3.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(2,0) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
macrocell41 U(2,0) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_3 2.243
macrocell41 U(2,0) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.497
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,0) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell37 U(2,0) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.247
macrocell37 U(2,0) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:mosi_pre_reg\/q \SPIM:BSPIM:mosi_pre_reg\/main_9 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,4) 1 \SPIM:BSPIM:mosi_pre_reg\ \SPIM:BSPIM:mosi_pre_reg\/clock_0 \SPIM:BSPIM:mosi_pre_reg\/q 1.250
macrocell36 U(2,4) 1 \SPIM:BSPIM:mosi_pre_reg\ \SPIM:BSPIM:mosi_pre_reg\/q \SPIM:BSPIM:mosi_pre_reg\/main_9 2.288
macrocell36 U(2,4) 1 \SPIM:BSPIM:mosi_pre_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_5 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(3,3) 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/clock_0 \SPIM:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_5 2.297
macrocell35 U(3,3) 1 \SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,4) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.944
macrocell30 U(3,4) 1 \SPIM:BSPIM:load_rx_data\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,2) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.900
statusicell2 U(3,1) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 3.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 2.612
macrocell23 U(3,2) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 3.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 2.622
macrocell20 U(3,2) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 3.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.622
macrocell21 U(3,2) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_3\/main_6 3.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_3\/main_6 2.622
macrocell22 U(3,2) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_8 3.248
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_8 2.628
macrocell23 U(3,2) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_0\/main_8 3.259
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_0\/main_8 2.639
macrocell20 U(3,2) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 3.259
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 2.639
macrocell21 U(3,2) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_3\/main_7 3.259
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_3\/main_7 2.639
macrocell22 U(3,2) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_1\/main_2 3.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:tx_state_1\/main_2 3.095
macrocell15 U(2,1) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_IntClock
Source Destination Delay (ns)
MISO_Flash(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 18.627
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO_Flash(0)_PAD MISO_Flash(0)_PAD MISO_Flash(0)/pad_in 0.000
iocell9 P12[2] 1 MISO_Flash(0) MISO_Flash(0)/pad_in MISO_Flash(0)/fb 7.315
Route 1 Net_19 MISO_Flash(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 5.342
datapathcell4 U(3,4) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 5.970
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPIM_IntClock
Source Destination Delay (ns)
Net_155/q MOSI_Flash(0)_PAD 31.720
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(3,0) 1 Net_155 Net_155/clock_0 Net_155/q 1.250
Route 1 Net_155 Net_155/q Net_65/main_0 4.629
macrocell9 U(3,3) 1 Net_65 Net_65/main_0 Net_65/q 3.350
Route 1 Net_65 Net_65/q MOSI_Flash(0)/pin_input 6.295
iocell8 P12[3] 1 MOSI_Flash(0) MOSI_Flash(0)/pin_input MOSI_Flash(0)/pad_out 16.196
Route 1 MOSI_Flash(0)_PAD MOSI_Flash(0)/pad_out MOSI_Flash(0)_PAD 0.000
Clock Clock path delay 0.000
Net_156/q SCLK_Flash(0)_PAD 23.199
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(3,4) 1 Net_156 Net_156/clock_0 Net_156/q 1.250
Route 1 Net_156 Net_156/q SCLK_Flash(0)/pin_input 6.898
iocell7 P4[0] 1 SCLK_Flash(0) SCLK_Flash(0)/pin_input SCLK_Flash(0)/pad_out 15.051
Route 1 SCLK_Flash(0)_PAD SCLK_Flash(0)/pad_out SCLK_Flash(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 34.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_115/main_0 5.265
macrocell1 U(2,3) 1 Net_115 Net_115/main_0 Net_115/q 3.350
Route 1 Net_115 Net_115/q Tx_1(0)/pin_input 7.578
iocell6 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000