Static Timing Analysis

Project : SLLD_test
Build Time : 05/21/19 18:29:59
Device : CY8C5268AXI-LP047
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 56.763 MHz
Debug_Uart_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 56.763 MHz
SPIM_IntClock CyMASTER_CLK 685.714 kHz 685.714 kHz 57.634 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL CyXTAL 8.000 MHz 8.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
RX(0)/fb \Debug_Uart:BUART:sRX:RxShifter:u0\/route_si 56.763 MHz 17.617 24.050
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_postpoll\/main_0 6.371
macrocell6 U(2,1) 1 \Debug_Uart:BUART:rx_postpoll\ \Debug_Uart:BUART:rx_postpoll\/main_0 \Debug_Uart:BUART:rx_postpoll\/q 3.350
Route 1 \Debug_Uart:BUART:rx_postpoll\ \Debug_Uart:BUART:rx_postpoll\/q \Debug_Uart:BUART:sRX:RxShifter:u0\/route_si 2.295
datapathcell3 U(2,1) 1 \Debug_Uart:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_state_0\/main_0 77.208 MHz 12.952 28.715
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_state_0\/main_0 7.311
macrocell19 U(2,0) 1 \Debug_Uart:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_state_2\/main_0 77.274 MHz 12.941 28.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_state_2\/main_0 7.300
macrocell22 U(2,0) 1 \Debug_Uart:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_status_3\/main_0 77.274 MHz 12.941 28.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_status_3\/main_0 7.300
macrocell27 U(2,0) 1 \Debug_Uart:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:pollcount_1\/main_0 83.250 MHz 12.012 29.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:pollcount_1\/main_0 6.371
macrocell25 U(2,1) 1 \Debug_Uart:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:pollcount_0\/main_0 83.250 MHz 12.012 29.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:pollcount_0\/main_0 6.371
macrocell26 U(2,1) 1 \Debug_Uart:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_last\/main_0 83.250 MHz 12.012 29.655
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_last\/main_0 6.371
macrocell28 U(2,1) 1 \Debug_Uart:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Debug_Uart:BUART:rx_state_2\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 56.954 MHz 17.558 1065.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,0) 1 \Debug_Uart:BUART:rx_state_2\ \Debug_Uart:BUART:rx_state_2\/clock_0 \Debug_Uart:BUART:rx_state_2\/q 1.250
Route 1 \Debug_Uart:BUART:rx_state_2\ \Debug_Uart:BUART:rx_state_2\/q \Debug_Uart:BUART:rx_counter_load\/main_3 5.360
macrocell5 U(3,0) 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/main_3 \Debug_Uart:BUART:rx_counter_load\/q 3.350
Route 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 2.238
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\Debug_Uart:BUART:tx_state_0\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.538 MHz 17.083 1066.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,2) 1 \Debug_Uart:BUART:tx_state_0\ \Debug_Uart:BUART:tx_state_0\/clock_0 \Debug_Uart:BUART:tx_state_0\/q 1.250
Route 1 \Debug_Uart:BUART:tx_state_0\ \Debug_Uart:BUART:tx_state_0\/q \Debug_Uart:BUART:counter_load_not\/main_1 3.380
macrocell2 U(2,2) 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/main_1 \Debug_Uart:BUART:counter_load_not\/q 3.350
Route 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\Debug_Uart:BUART:tx_state_1\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.572 MHz 17.073 1066.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,2) 1 \Debug_Uart:BUART:tx_state_1\ \Debug_Uart:BUART:tx_state_1\/clock_0 \Debug_Uart:BUART:tx_state_1\/q 1.250
Route 1 \Debug_Uart:BUART:tx_state_1\ \Debug_Uart:BUART:tx_state_1\/q \Debug_Uart:BUART:counter_load_not\/main_0 3.370
macrocell2 U(2,2) 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/main_0 \Debug_Uart:BUART:counter_load_not\/q 3.350
Route 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\Debug_Uart:BUART:tx_state_2\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.285 MHz 16.588 1066.745
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,2) 1 \Debug_Uart:BUART:tx_state_2\ \Debug_Uart:BUART:tx_state_2\/clock_0 \Debug_Uart:BUART:tx_state_2\/q 1.250
Route 1 \Debug_Uart:BUART:tx_state_2\ \Debug_Uart:BUART:tx_state_2\/q \Debug_Uart:BUART:counter_load_not\/main_3 2.885
macrocell2 U(2,2) 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/main_3 \Debug_Uart:BUART:counter_load_not\/q 3.350
Route 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.838 MHz 16.437 1066.896
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\ \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/clock \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \Debug_Uart:BUART:tx_bitclk_enable_pre\ \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \Debug_Uart:BUART:counter_load_not\/main_2 3.794
macrocell2 U(2,2) 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/main_2 \Debug_Uart:BUART:counter_load_not\/q 3.350
Route 1 \Debug_Uart:BUART:counter_load_not\ \Debug_Uart:BUART:counter_load_not\/q \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \Debug_Uart:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\Debug_Uart:BUART:rx_state_0\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 61.690 MHz 16.210 1067.123
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,0) 1 \Debug_Uart:BUART:rx_state_0\ \Debug_Uart:BUART:rx_state_0\/clock_0 \Debug_Uart:BUART:rx_state_0\/q 1.250
Route 1 \Debug_Uart:BUART:rx_state_0\ \Debug_Uart:BUART:rx_state_0\/q \Debug_Uart:BUART:rx_counter_load\/main_1 4.012
macrocell5 U(3,0) 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/main_1 \Debug_Uart:BUART:rx_counter_load\/q 3.350
Route 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 2.238
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\Debug_Uart:BUART:rx_state_3\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 64.458 MHz 15.514 1067.819
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,0) 1 \Debug_Uart:BUART:rx_state_3\ \Debug_Uart:BUART:rx_state_3\/clock_0 \Debug_Uart:BUART:rx_state_3\/q 1.250
Route 1 \Debug_Uart:BUART:rx_state_3\ \Debug_Uart:BUART:rx_state_3\/q \Debug_Uart:BUART:rx_counter_load\/main_2 3.316
macrocell5 U(3,0) 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/main_2 \Debug_Uart:BUART:rx_counter_load\/q 3.350
Route 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 2.238
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\Debug_Uart:BUART:tx_ctrl_mark_last\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 64.537 MHz 15.495 1067.838
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,0) 1 \Debug_Uart:BUART:tx_ctrl_mark_last\ \Debug_Uart:BUART:tx_ctrl_mark_last\/clock_0 \Debug_Uart:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \Debug_Uart:BUART:tx_ctrl_mark_last\ \Debug_Uart:BUART:tx_ctrl_mark_last\/q \Debug_Uart:BUART:rx_counter_load\/main_0 3.297
macrocell5 U(3,0) 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/main_0 \Debug_Uart:BUART:rx_counter_load\/q 3.350
Route 1 \Debug_Uart:BUART:rx_counter_load\ \Debug_Uart:BUART:rx_counter_load\/q \Debug_Uart:BUART:sRX:RxBitCounter\/load 2.238
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\Debug_Uart:BUART:pollcount_1\/q \Debug_Uart:BUART:sRX:RxShifter:u0\/route_si 71.746 MHz 13.938 1069.395
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,1) 1 \Debug_Uart:BUART:pollcount_1\ \Debug_Uart:BUART:pollcount_1\/clock_0 \Debug_Uart:BUART:pollcount_1\/q 1.250
Route 1 \Debug_Uart:BUART:pollcount_1\ \Debug_Uart:BUART:pollcount_1\/q \Debug_Uart:BUART:rx_postpoll\/main_1 3.573
macrocell6 U(2,1) 1 \Debug_Uart:BUART:rx_postpoll\ \Debug_Uart:BUART:rx_postpoll\/main_1 \Debug_Uart:BUART:rx_postpoll\/q 3.350
Route 1 \Debug_Uart:BUART:rx_postpoll\ \Debug_Uart:BUART:rx_postpoll\/q \Debug_Uart:BUART:sRX:RxShifter:u0\/route_si 2.295
datapathcell3 U(2,1) 1 \Debug_Uart:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \Debug_Uart:BUART:sRX:RxSts\/status_4 71.788 MHz 13.930 1069.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,1) 1 \Debug_Uart:BUART:sRX:RxShifter:u0\ \Debug_Uart:BUART:sRX:RxShifter:u0\/clock \Debug_Uart:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \Debug_Uart:BUART:rx_fifofull\ \Debug_Uart:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \Debug_Uart:BUART:rx_status_4\/main_1 2.290
macrocell7 U(2,1) 1 \Debug_Uart:BUART:rx_status_4\ \Debug_Uart:BUART:rx_status_4\/main_1 \Debug_Uart:BUART:rx_status_4\/q 3.350
Route 1 \Debug_Uart:BUART:rx_status_4\ \Debug_Uart:BUART:rx_status_4\/q \Debug_Uart:BUART:sRX:RxSts\/status_4 4.210
statusicell2 U(2,1) 1 \Debug_Uart:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 1458.33ns(685.714 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 57.634 MHz 17.351 1440.982
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.800
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 6.411
datapathcell4 U(3,3) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 57.647 MHz 17.347 1440.986
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.796
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 6.411
datapathcell4 U(3,3) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 57.667 MHz 17.341 1440.992
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.790
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 6.411
datapathcell4 U(3,3) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 57.697 MHz 17.332 1441.001
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.781
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 6.411
datapathcell4 U(3,3) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 58.241 MHz 17.170 1441.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.619
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 6.411
datapathcell4 U(3,3) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:TxStsReg\/status_3 60.698 MHz 16.475 1441.858
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.800
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 7.885
statusicell3 U(3,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:TxStsReg\/status_3 60.713 MHz 16.471 1441.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.796
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 7.885
statusicell3 U(3,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 60.735 MHz 16.465 1441.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.790
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 7.885
statusicell3 U(3,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:TxStsReg\/status_3 60.768 MHz 16.456 1441.877
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.781
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 7.885
statusicell3 U(3,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:TxStsReg\/status_3 61.372 MHz 16.294 1442.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 2.619
macrocell9 U(3,3) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 7.885
statusicell3 U(3,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
RX(0)/fb \Debug_Uart:BUART:pollcount_1\/main_0 8.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:pollcount_1\/main_0 6.371
macrocell25 U(2,1) 1 \Debug_Uart:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:pollcount_0\/main_0 8.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:pollcount_0\/main_0 6.371
macrocell26 U(2,1) 1 \Debug_Uart:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_last\/main_0 8.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_last\/main_0 6.371
macrocell28 U(2,1) 1 \Debug_Uart:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_state_2\/main_0 9.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_state_2\/main_0 7.300
macrocell22 U(2,0) 1 \Debug_Uart:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_status_3\/main_0 9.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_status_3\/main_0 7.300
macrocell27 U(2,0) 1 \Debug_Uart:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:rx_state_0\/main_0 9.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_state_0\/main_0 7.311
macrocell19 U(2,0) 1 \Debug_Uart:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \Debug_Uart:BUART:sRX:RxShifter:u0\/route_si 14.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P1[4] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.131
Route 1 Net_120 RX(0)/fb \Debug_Uart:BUART:rx_postpoll\/main_0 6.371
macrocell6 U(2,1) 1 \Debug_Uart:BUART:rx_postpoll\ \Debug_Uart:BUART:rx_postpoll\/main_0 \Debug_Uart:BUART:rx_postpoll\/q 3.350
Route 1 \Debug_Uart:BUART:rx_postpoll\ \Debug_Uart:BUART:rx_postpoll\/q \Debug_Uart:BUART:sRX:RxShifter:u0\/route_si 2.295
datapathcell3 U(2,1) 1 \Debug_Uart:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Debug_Uart:BUART:rx_status_3\/q \Debug_Uart:BUART:sRX:RxSts\/status_3 2.126
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,0) 1 \Debug_Uart:BUART:rx_status_3\ \Debug_Uart:BUART:rx_status_3\/clock_0 \Debug_Uart:BUART:rx_status_3\/q 1.250
Route 1 \Debug_Uart:BUART:rx_status_3\ \Debug_Uart:BUART:rx_status_3\/q \Debug_Uart:BUART:sRX:RxSts\/status_3 2.876
statusicell2 U(2,1) 1 \Debug_Uart:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_load_fifo\/main_7 3.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \Debug_Uart:BUART:rx_count_4\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_load_fifo\/main_7 2.551
macrocell20 U(2,0) 1 \Debug_Uart:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_state_2\/main_8 3.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \Debug_Uart:BUART:rx_count_4\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_state_2\/main_8 2.551
macrocell22 U(2,0) 1 \Debug_Uart:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_state_0\/main_8 3.178
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \Debug_Uart:BUART:rx_count_4\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_state_0\/main_8 2.558
macrocell19 U(2,0) 1 \Debug_Uart:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_state_3\/main_7 3.178
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \Debug_Uart:BUART:rx_count_4\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_4 \Debug_Uart:BUART:rx_state_3\/main_7 2.558
macrocell21 U(2,0) 1 \Debug_Uart:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_6 \Debug_Uart:BUART:rx_load_fifo\/main_5 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \Debug_Uart:BUART:rx_count_6\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_6 \Debug_Uart:BUART:rx_load_fifo\/main_5 2.684
macrocell20 U(2,0) 1 \Debug_Uart:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_6 \Debug_Uart:BUART:rx_state_2\/main_6 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \Debug_Uart:BUART:rx_count_6\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_6 \Debug_Uart:BUART:rx_state_2\/main_6 2.684
macrocell22 U(2,0) 1 \Debug_Uart:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_5 \Debug_Uart:BUART:rx_load_fifo\/main_6 3.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \Debug_Uart:BUART:rx_count_5\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_5 \Debug_Uart:BUART:rx_load_fifo\/main_6 2.688
macrocell20 U(2,0) 1 \Debug_Uart:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_5 \Debug_Uart:BUART:rx_state_2\/main_7 3.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \Debug_Uart:BUART:rx_count_5\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_5 \Debug_Uart:BUART:rx_state_2\/main_7 2.688
macrocell22 U(2,0) 1 \Debug_Uart:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\Debug_Uart:BUART:sRX:RxBitCounter\/count_5 \Debug_Uart:BUART:rx_state_0\/main_7 3.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \Debug_Uart:BUART:sRX:RxBitCounter\ \Debug_Uart:BUART:sRX:RxBitCounter\/clock \Debug_Uart:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \Debug_Uart:BUART:rx_count_5\ \Debug_Uart:BUART:sRX:RxBitCounter\/count_5 \Debug_Uart:BUART:rx_state_0\/main_7 2.720
macrocell19 U(2,0) 1 \Debug_Uart:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_4 Net_65/main_5 3.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 Net_65/main_5 2.619
macrocell29 U(3,3) 1 Net_65 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_cond\/main_3 3.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 0.620
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_cond\/main_3 2.630
macrocell34 U(3,3) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 Net_65/main_6 3.401
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 Net_65/main_6 2.781
macrocell29 U(3,3) 1 Net_65 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 Net_65/main_9 3.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 Net_65/main_9 2.790
macrocell29 U(3,3) 1 Net_65 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 Net_65/main_8 3.416
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 Net_65/main_8 2.796
macrocell29 U(3,3) 1 Net_65 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_cond\/main_7 3.418
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_cond\/main_7 2.798
macrocell34 U(3,3) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 Net_65/main_7 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 Net_65/main_7 2.800
macrocell29 U(3,3) 1 Net_65 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_cond\/main_4 3.425
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_cond\/main_4 2.805
macrocell34 U(3,3) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_cond\/main_6 3.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_cond\/main_6 2.816
macrocell34 U(3,3) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_cond\/main_5 3.441
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_cond\/main_5 2.821
macrocell34 U(3,3) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_IntClock
Source Destination Delay (ns)
MISO(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 15.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MISO(0)_PAD MISO(0)_PAD MISO(0)/pad_in 0.000
iocell9 P12[2] 1 MISO(0) MISO(0)/pad_in MISO(0)/fb 7.315
Route 1 Net_19 MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 4.739
datapathcell4 U(3,3) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ Debug_Uart_IntClock
Source Destination Delay (ns)
\Debug_Uart:BUART:txn\/q TX(0)_PAD 31.667
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,2) 1 \Debug_Uart:BUART:txn\ \Debug_Uart:BUART:txn\/clock_0 \Debug_Uart:BUART:txn\/q 1.250
Route 1 \Debug_Uart:BUART:txn\ \Debug_Uart:BUART:txn\/q Net_115/main_0 4.522
macrocell1 U(2,1) 1 Net_115 Net_115/main_0 Net_115/q 3.350
Route 1 Net_115 Net_115/q TX(0)/pin_input 7.203
iocell6 P1[5] 1 TX(0) TX(0)/pin_input TX(0)/pad_out 15.342
Route 1 TX(0)_PAD TX(0)/pad_out TX(0)_PAD 0.000
Clock Clock path delay 0.000
+ SPIM_IntClock
Source Destination Delay (ns)
Net_65/q MOSI(0)_PAD 24.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(3,3) 1 Net_65 Net_65/clock_0 Net_65/q 1.250
Route 1 Net_65 Net_65/q MOSI(0)/pin_input 6.588
iocell8 P12[3] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 16.196
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_156/q SCLK(0)_PAD 23.996
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(3,3) 1 Net_156 Net_156/clock_0 Net_156/q 1.250
Route 1 Net_156 Net_156/q SCLK(0)/pin_input 7.695
iocell7 P4[0] 1 SCLK(0) SCLK(0)/pin_input SCLK(0)/pad_out 15.051
Route 1 SCLK(0)_PAD SCLK(0)/pad_out SCLK(0)_PAD 0.000
Clock Clock path delay 0.000