Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.6 (WebPack) - P.68d Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx25
Project ID (random number) b5cc4b0bc89a4d76aede1baf3c8f7bc5.38814CD2A3CF498A826558DD5221B2BC.7 Target Package: ftg256
Registration ID 210805034_0_0_738 Target Speed: -3
Date Generated 2013-10-11T11:04:10 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz CPU Speed 2594 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i5-3320M CPU @ 2.60GHz CPU Speed 2594 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 4-bit comparator greater=1
Counters=2
  • 17-bit up counter=1
  • 4-bit up counter=1
Registers=3
  • Flip-Flops=3
MiscellaneousStatistics
  • AGG_BONDED_IO=29
  • AGG_IO=29
  • AGG_LOCED_IO=28
  • AGG_SLICE=18
  • NUM_BONDED_IOB=29
  • NUM_BSFULL=21
  • NUM_BSLUTONLY=17
  • NUM_BSUSED=38
  • NUM_BUFG=2
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_DCM=1
  • NUM_IOB_FF=19
  • NUM_LOCED_IOB=28
  • NUM_LOGIC_O5ANDO6=4
  • NUM_LOGIC_O5ONLY=14
  • NUM_LOGIC_O6ONLY=19
  • NUM_LUT_RT_DRIVES_CARRY4=1
  • NUM_LUT_RT_EXO6=1
  • NUM_LUT_RT_O6=14
  • NUM_OLOGIC2=19
  • NUM_SLICEL=4
  • NUM_SLICEX=14
  • NUM_SLICE_CARRY4=4
  • NUM_SLICE_CONTROLSET=3
  • NUM_SLICE_CYINIT=57
  • NUM_SLICE_FF=22
  • NUM_SLICE_UNUSEDCTRL=4
  • NUM_UNUSABLE_FF_BELS=10
NetStatistics
  • NumNets_Active=120
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEIN=20
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=8
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=34
  • NumNodesOfType_Active_CLKPINFEED=14
  • NumNodesOfType_Active_CNTRLPIN=60
  • NumNodesOfType_Active_DOUBLE=85
  • NumNodesOfType_Active_GENERIC=32
  • NumNodesOfType_Active_GLOBAL=35
  • NumNodesOfType_Active_INPUT=7
  • NumNodesOfType_Active_IOBIN2OUT=23
  • NumNodesOfType_Active_IOBOUTPUT=24
  • NumNodesOfType_Active_LUTINPUT=84
  • NumNodesOfType_Active_OUTBOUND=64
  • NumNodesOfType_Active_OUTPUT=74
  • NumNodesOfType_Active_PADINPUT=20
  • NumNodesOfType_Active_PADOUTPUT=3
  • NumNodesOfType_Active_PINBOUNCE=31
  • NumNodesOfType_Active_PINFEED=207
  • NumNodesOfType_Active_PINFEED1=1
  • NumNodesOfType_Active_PINFEED2=21
  • NumNodesOfType_Active_QUAD=236
  • NumNodesOfType_Active_REGINPUT=1
  • NumNodesOfType_Active_SINGLE=84
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_GENERIC=2
  • NumNodesOfType_Vcc_HVCCOUT=8
  • NumNodesOfType_Vcc_IOBIN2OUT=3
  • NumNodesOfType_Vcc_IOBOUTPUT=2
  • NumNodesOfType_Vcc_KVCCOUT=1
  • NumNodesOfType_Vcc_LUTINPUT=18
  • NumNodesOfType_Vcc_PADINPUT=2
  • NumNodesOfType_Vcc_PINFEED=22
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=14
  • IOB-IOBS=15
  • SLICEX-SLICEL=1
  • SLICEX-SLICEM=3
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • CARRY4=4
  • DCM=1
  • DCM_DCM=1
  • FF_SR=2
  • HARD0=1
  • IOB=29
  • IOB_IMUX=4
  • IOB_INBUF=4
  • IOB_OUTBUF=25
  • LUT5=18
  • LUT6=38
  • OLOGIC2=19
  • OLOGIC2_OUTFF=19
  • PAD=29
  • REG_SR=20
  • SLICEL=4
  • SLICEX=14
 
Configuration Data
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2.0:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
FF_SR
  • CK=[CK:2] [CK_INV:0]
  • SRINIT=[SRINIT0:2]
  • SYNC_ATTR=[ASYNC:2]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:25]
  • SLEW=[SLOW:25]
  • SUSPEND=[3STATE:25]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:19]
  • CLK1=[CLK1:0] [CLK1_INV:1]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:19]
  • CK1=[CK1_INV:1] [CK1:0]
  • DDR_ALIGNMENT=[NONE:1]
  • OUTFFTYPE=[FF:18] [DDR:1]
  • SRINIT_OQ=[0:18] [1:1]
  • SRTYPE_OQ=[ASYNC:18] [SYNC:1]
REG_SR
  • CK=[CK:20] [CK_INV:0]
  • LATCH_OR_FF=[FF:20]
  • SRINIT=[SRINIT0:20]
  • SYNC_ATTR=[ASYNC:20]
SLICEL
  • CLK=[CLK:1] [CLK_INV:0]
SLICEX
  • CLK=[CLK:13] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
CARRY4
  • CIN=3
  • CO3=3
  • CYINIT=1
  • DI0=4
  • DI1=4
  • DI2=4
  • DI3=3
  • O0=4
  • O1=4
  • O2=4
  • O3=4
  • S0=4
  • S1=4
  • S2=4
  • S3=4
DCM
  • CLK0=1
  • CLK180=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLK180=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
FF_SR
  • CE=1
  • CK=2
  • D=2
  • Q=2
  • SR=2
HARD0
  • 0=1
IOB
  • I=4
  • O=25
  • PAD=29
IOB_IMUX
  • I=4
  • OUT=4
IOB_INBUF
  • OUT=4
  • PAD=4
IOB_OUTBUF
  • IN=25
  • OUT=25
LUT5
  • A1=1
  • A2=3
  • A3=3
  • A4=1
  • A5=1
  • O5=18
LUT6
  • A2=2
  • A3=3
  • A4=21
  • A5=35
  • A6=37
  • O6=38
OLOGIC2
  • CLK0=19
  • CLK1=1
  • D1=19
  • D2=1
  • OCE=17
  • OQ=19
  • SR=19
OLOGIC2_OUTFF
  • CE=17
  • CK0=19
  • CK1=1
  • D1=19
  • D2=1
  • Q=19
  • SR=19
PAD
  • PAD=29
REG_SR
  • CE=19
  • CK=20
  • D=20
  • Q=20
  • SR=20
SLICEL
  • A5=4
  • A6=4
  • AMUX=4
  • B5=4
  • B6=4
  • BMUX=4
  • C5=4
  • C6=4
  • CE=1
  • CIN=3
  • CLK=1
  • CMUX=4
  • COUT=3
  • D5=3
  • D6=4
  • DMUX=4
  • DQ=1
  • DX=1
  • SR=1
SLICEX
  • A=10
  • A4=11
  • A5=10
  • A6=10
  • AQ=10
  • B=2
  • B1=1
  • B2=1
  • B3=1
  • B4=3
  • B5=2
  • B6=3
  • BMUX=1
  • BQ=3
  • C2=1
  • C3=1
  • C4=1
  • C5=1
  • C6=1
  • CE=11
  • CLK=13
  • CMUX=1
  • CQ=1
  • D=7
  • D2=2
  • D3=2
  • D4=6
  • D5=7
  • D6=7
  • DMUX=1
  • DQ=5
  • SR=13
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 1 1 0 0 0 0 0
map 1 1 0 0 0 0 0
ngdbuild 1 1 0 0 0 0 0
par 1 1 0 0 0 0 0
trce 1 1 0 0 0 0 0
xst 1 1 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-03-26T11:38:06
PROP_intWbtProjectID=38814CD2A3CF498A826558DD5221B2BC PROP_intWbtProjectIteration=7
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_xstPackIORegister=Yes
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx25 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=ftg256 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=Verilog
FILE_UCF=1 FILE_VERILOG=2
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=20.833 clkin2_period=20.833 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=4 primtype_sel=DCM_SP
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=true use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1 XST_NUM_ODDR2=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=3 NGDBUILD_NUM_FDCE=36
NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=3 NGDBUILD_NUM_LUT3=19
NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_OBUF=25
NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=3 NGDBUILD_NUM_FDCE=36
NGDBUILD_NUM_FDP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=3 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT1=15 NGDBUILD_NUM_LUT2=3 NGDBUILD_NUM_LUT3=19
NGDBUILD_NUM_LUT4=1 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_MUXCY=15 NGDBUILD_NUM_OBUF=25
NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=16
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx25-3-ftg256
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=True
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5