clk_wiz_v3_6 Project Status | |||
Project File: | fx2lp_streamOUT_proj.xise | Parser Errors: | No Errors |
Module Name: | clk_wiz_v3_6 | Implementation State: | New |
Target Device: | xc6slx25-3ftg256 |
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Product Version: | ISE 14.4 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Fri Mar 15 12:24:07 2013 | |
WebTalk Log File | Current | Fri Mar 15 12:24:17 2013 |