fx2lp_slaveFIFO2b_loopback_fpga_top Project Status (03/26/2013 - 13:00:33)
Project File: fx2lp_loopback_proj.xise Parser Errors: No Errors
Module Name: fx2lp_slaveFIFO2b_loopback_fpga_top Implementation State: Programming File Generated
Target Device: xc6slx25-3ftg256
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
10 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 51 30,064 1%  
    Number used as Flip Flops 51      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 102 15,032 1%  
    Number used as logic 102 15,032 1%  
        Number using O6 output only 75      
        Number using O5 output only 0      
        Number using O5 and O6 27      
        Number used as ROM 0      
    Number used as Memory 0 3,664 0%  
Number of occupied Slices 42 3,758 1%  
Number of MUXCYs used 24 7,516 1%  
Number of LUT Flip Flop pairs used 102      
    Number with an unused Flip Flop 52 102 50%  
    Number with an unused LUT 0 102 0%  
    Number of fully used LUT-FF pairs 50 102 49%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
5 30,064 1%  
Number of bonded IOBs 26 186 13%  
    Number of LOCed IOBs 26 26 100%  
    IOB Flip Flops 3      
Number of RAMB16BWERs 0 52 0%  
Number of RAMB8BWERs 1 104 1%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 1 32 3%  
    Number used as BUFIO2FBs 1      
    Number used as BUFIO2FB_2CLKs 0      
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 0 272 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 272 0%  
Number of OLOGIC2/OSERDES2s 3 272 1%  
    Number used as OLOGIC2s 3      
    Number used as OSERDES2s 0      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 160 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 38 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.87      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Mar 26 13:48:18 201308 Warnings (0 new)4 Infos (0 new)
Translation ReportCurrentTue Mar 26 13:48:24 2013000
Map ReportCurrentTue Mar 26 13:48:38 201301 Warning (0 new)6 Infos (0 new)
Place and Route ReportCurrentTue Mar 26 13:48:52 2013003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Mar 26 13:49:00 2013004 Infos (0 new)
Bitgen ReportCurrentTue Mar 26 13:49:16 201301 Warning (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentTue Mar 26 13:49:16 2013
WebTalk Log FileCurrentTue Mar 26 13:49:22 2013

Date Generated: 10/03/2013 - 21:43:55