Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (WebPack) - P.49d Target Family: Spartan6
OS Platform: NT Target Device: xc6slx25
Project ID (random number) e333ae5154d542c9a02c9b4e98c23735.DA5799D64A8B44F68BD5C7E6F89F39D0.14 Target Package: ftg256
Registration ID __0_0_0 Target Speed: -3
Date Generated 2013-03-26T14:35:53 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz CPU Speed 2194 MHz
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz CPU Speed 2194 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=4
  • 10-bit updown loadable accumulator=2
  • 9-bit up loadable accumulator=2
Adders/Subtractors=3
  • 10-bit addsub=2
  • 9-bit adder=1
Comparators=1
  • 4-bit comparator greater=1
Counters=1
  • 4-bit up counter=1
FSMs=1 Multiplexers=11
  • 10-bit 2-to-1 multiplexer=8
  • 16-bit 2-to-1 multiplexer=1
  • 9-bit 2-to-1 multiplexer=2
RAMs=1
  • 512x16-bit dual-port block RAM=1
Registers=5
  • Flip-Flops=5
MiscellaneousStatistics
  • AGG_BONDED_IO=28
  • AGG_IO=28
  • AGG_LOCED_IO=27
  • AGG_SLICE=38
  • NUM_BONDED_IOB=28
  • NUM_BSFULL=46
  • NUM_BSLUTONLY=39
  • NUM_BSREGONLY=7
  • NUM_BSUSED=92
  • NUM_BUFG=2
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_DCM=1
  • NUM_IOB_FF=4
  • NUM_LOCED_IOB=27
  • NUM_LOGIC_O5ANDO6=32
  • NUM_LOGIC_O6ONLY=53
  • NUM_OLOGIC2=4
  • NUM_RAMB8BWER=1
  • NUM_SLICEL=6
  • NUM_SLICEX=32
  • NUM_SLICE_CARRY4=6
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=117
  • NUM_SLICE_FF=53
  • NUM_SLICE_UNUSEDCTRL=20
  • NUM_UNUSABLE_FF_BELS=11
NetStatistics
  • NumNets_Active=187
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=3
  • NumNodesOfType_Active_BOUNCEIN=26
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=6
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=23
  • NumNodesOfType_Active_CLKPINFEED=12
  • NumNodesOfType_Active_CNTRLPIN=23
  • NumNodesOfType_Active_DOUBLE=212
  • NumNodesOfType_Active_GENERIC=83
  • NumNodesOfType_Active_GLOBAL=30
  • NumNodesOfType_Active_INPUT=45
  • NumNodesOfType_Active_IOBIN2OUT=57
  • NumNodesOfType_Active_IOBOUTPUT=59
  • NumNodesOfType_Active_LUTINPUT=410
  • NumNodesOfType_Active_OUTBOUND=181
  • NumNodesOfType_Active_OUTPUT=145
  • NumNodesOfType_Active_PADINPUT=39
  • NumNodesOfType_Active_PADOUTPUT=19
  • NumNodesOfType_Active_PINBOUNCE=77
  • NumNodesOfType_Active_PINFEED=532
  • NumNodesOfType_Active_PINFEED1=1
  • NumNodesOfType_Active_PINFEED2=6
  • NumNodesOfType_Active_QUAD=440
  • NumNodesOfType_Active_REGINPUT=10
  • NumNodesOfType_Active_SINGLE=267
  • NumNodesOfType_Gnd_BOUNCEIN=6
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_GENERIC=1
  • NumNodesOfType_Gnd_HGNDOUT=6
  • NumNodesOfType_Gnd_INPUT=9
  • NumNodesOfType_Gnd_IOBIN2OUT=1
  • NumNodesOfType_Gnd_IOBINPUT=1
  • NumNodesOfType_Gnd_IOBOUTPUT=1
  • NumNodesOfType_Gnd_OUTBOUND=3
  • NumNodesOfType_Gnd_OUTPUT=4
  • NumNodesOfType_Gnd_PADINPUT=1
  • NumNodesOfType_Gnd_PINBOUNCE=3
  • NumNodesOfType_Gnd_PINFEED=15
  • NumNodesOfType_Gnd_SINGLE=3
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_GENERIC=1
  • NumNodesOfType_Vcc_HVCCOUT=17
  • NumNodesOfType_Vcc_INPUT=2
  • NumNodesOfType_Vcc_IOBIN2OUT=3
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=3
  • NumNodesOfType_Vcc_LUTINPUT=32
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINFEED=38
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=14
  • IOB-IOBS=14
  • SLICEL-SLICEM=6
  • SLICEX-SLICEL=14
  • SLICEX-SLICEM=4
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • CARRY4=6
  • DCM=1
  • DCM_DCM=1
  • FF_SR=2
  • IOB=28
  • IOB_IMUX=19
  • IOB_INBUF=19
  • IOB_OUTBUF=25
  • LUT5=32
  • LUT6=85
  • OLOGIC2=4
  • OLOGIC2_OUTFF=4
  • PAD=28
  • RAMB8BWER=1
  • RAMB8BWER_RAMB8BWER=1
  • REG_SR=51
  • SLICEL=6
  • SLICEX=32
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
  • JTAG_TEST=[0:1]
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2.0:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
FF_SR
  • CK=[CK:2] [CK_INV:0]
  • SRINIT=[SRINIT0:2]
  • SYNC_ATTR=[ASYNC:2]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:25]
  • SLEW=[SLOW:25]
  • SUSPEND=[3STATE:25]
LUT_OR_MEM5
  • CLK=[CLK:10] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:10]
  • RAMMODE=[SRL16:10]
LUT_OR_MEM6
  • CLK=[CLK:71] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:71]
  • RAMMODE=[SRL16:36] [SRL32:35]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:4]
  • CLK1=[CLK1:0] [CLK1_INV:1]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:4]
  • CK1=[CK1_INV:1] [CK1:0]
  • DDR_ALIGNMENT=[NONE:1]
  • OUTFFTYPE=[FF:3] [DDR:1]
  • SRINIT_OQ=[0:3] [1:1]
  • SRTYPE_OQ=[ASYNC:3] [SYNC:1]
RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • DATA_WIDTH_A=[9:2]
  • DATA_WIDTH_B=[9:2]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • EN_RSTRAM_A=[FALSE:2]
  • EN_RSTRAM_B=[FALSE:2]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[18:1]
  • DATA_WIDTH_B=[18:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[TRUE:1]
  • EN_RSTRAM_B=[TRUE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[READ_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
REG_SR
  • CK=[CK:51] [CK_INV:0]
  • LATCH_OR_FF=[FF:51]
  • SRINIT=[SRINIT0:50] [SRINIT1:1]
  • SYNC_ATTR=[ASYNC:51]
SLICEL
  • CLK=[CLK:6] [CLK_INV:0]
SLICEM
  • CLK=[CLK:32] [CLK_INV:0]
SLICEX
  • CLK=[CLK:12] [CLK_INV:0]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
CARRY4
  • CIN=4
  • CO3=4
  • CYINIT=2
  • DI0=6
  • DI1=4
  • DI2=4
  • DI3=4
  • O0=6
  • O1=6
  • O2=4
  • O3=4
  • S0=6
  • S1=6
  • S2=4
  • S3=4
DCM
  • CLK0=1
  • CLK180=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLK180=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
FF_SR
  • CE=2
  • CK=2
  • D=2
  • Q=2
  • SR=2
HARD1
  • 1=10
IOB
  • I=19
  • O=25
  • PAD=28
  • T=16
IOB_IMUX
  • I=19
  • OUT=19
IOB_INBUF
  • OUT=19
  • PAD=19
IOB_OUTBUF
  • IN=25
  • OUT=25
  • TRI=16
LUT5
  • A1=15
  • A2=21
  • A3=11
  • A4=29
  • A5=32
  • O5=32
LUT6
  • A1=41
  • A2=69
  • A3=75
  • A4=81
  • A5=82
  • A6=84
  • O6=85
LUT_OR_MEM5
  • A1=10
  • A2=10
  • A3=11
  • A4=11
  • A5=10
  • CLK=10
  • DI1=10
  • O5=11
  • WE=10
LUT_OR_MEM6
  • A1=71
  • A2=71
  • A3=71
  • A4=72
  • A5=72
  • A6=72
  • CLK=71
  • DI1=35
  • DI2=36
  • MC31=57
  • O6=72
  • WE=71
OLOGIC2
  • CLK0=4
  • CLK1=1
  • D1=4
  • D2=1
  • OCE=2
  • OQ=4
  • SR=4
OLOGIC2_OUTFF
  • CE=2
  • CK0=4
  • CK1=1
  • D1=4
  • D2=1
  • Q=4
  • SR=4
PAD
  • PAD=28
RAMB16BWER
  • ADDRA0=2
  • ADDRA1=2
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=2
  • ADDRB1=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=2
  • DIA17=2
  • DIA18=2
  • DIA19=2
  • DIA2=2
  • DIA20=2
  • DIA21=2
  • DIA22=2
  • DIA23=2
  • DIA24=2
  • DIA25=2
  • DIA26=2
  • DIA27=2
  • DIA28=2
  • DIA29=2
  • DIA3=2
  • DIA30=2
  • DIA31=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=2
  • DIB1=2
  • DIB10=2
  • DIB11=2
  • DIB12=2
  • DIB13=2
  • DIB14=2
  • DIB15=2
  • DIB16=2
  • DIB17=2
  • DIB18=2
  • DIB19=2
  • DIB2=2
  • DIB20=2
  • DIB21=2
  • DIB22=2
  • DIB23=2
  • DIB24=2
  • DIB25=2
  • DIB26=2
  • DIB27=2
  • DIB28=2
  • DIB29=2
  • DIB3=2
  • DIB30=2
  • DIB31=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIB8=2
  • DIB9=2
  • DIPA0=2
  • DIPA1=2
  • DIPA2=2
  • DIPA3=2
  • DIPB0=2
  • DIPB1=2
  • DIPB2=2
  • DIPB3=2
  • DOA0=2
  • DOA1=2
  • DOA2=2
  • DOA3=2
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOPA0=2
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
RAMB16BWER_RAMB16BWER
  • ADDRA0=2
  • ADDRA1=2
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=2
  • ADDRB1=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=2
  • DIA17=2
  • DIA18=2
  • DIA19=2
  • DIA2=2
  • DIA20=2
  • DIA21=2
  • DIA22=2
  • DIA23=2
  • DIA24=2
  • DIA25=2
  • DIA26=2
  • DIA27=2
  • DIA28=2
  • DIA29=2
  • DIA3=2
  • DIA30=2
  • DIA31=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=2
  • DIB1=2
  • DIB10=2
  • DIB11=2
  • DIB12=2
  • DIB13=2
  • DIB14=2
  • DIB15=2
  • DIB16=2
  • DIB17=2
  • DIB18=2
  • DIB19=2
  • DIB2=2
  • DIB20=2
  • DIB21=2
  • DIB22=2
  • DIB23=2
  • DIB24=2
  • DIB25=2
  • DIB26=2
  • DIB27=2
  • DIB28=2
  • DIB29=2
  • DIB3=2
  • DIB30=2
  • DIB31=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIB8=2
  • DIB9=2
  • DIPA0=2
  • DIPA1=2
  • DIPA2=2
  • DIPA3=2
  • DIPB0=2
  • DIPB1=2
  • DIPB2=2
  • DIPB3=2
  • DOA0=2
  • DOA1=2
  • DOA2=2
  • DOA3=2
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOPA0=2
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DOBDO0=1
  • DOBDO1=1
  • DOBDO10=1
  • DOBDO11=1
  • DOBDO12=1
  • DOBDO13=1
  • DOBDO14=1
  • DOBDO15=1
  • DOBDO2=1
  • DOBDO3=1
  • DOBDO4=1
  • DOBDO5=1
  • DOBDO6=1
  • DOBDO7=1
  • DOBDO8=1
  • DOBDO9=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DOBDO0=1
  • DOBDO1=1
  • DOBDO10=1
  • DOBDO11=1
  • DOBDO12=1
  • DOBDO13=1
  • DOBDO14=1
  • DOBDO15=1
  • DOBDO2=1
  • DOBDO3=1
  • DOBDO4=1
  • DOBDO5=1
  • DOBDO6=1
  • DOBDO7=1
  • DOBDO8=1
  • DOBDO9=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
REG_SR
  • CE=2
  • CK=51
  • D=51
  • Q=51
  • SR=51
SELMUX2_1
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL
  • A1=4
  • A2=6
  • A3=6
  • A4=6
  • A5=6
  • A6=6
  • AQ=6
  • AX=2
  • B1=2
  • B2=5
  • B3=6
  • B4=6
  • B5=6
  • B6=6
  • BQ=6
  • C1=2
  • C2=4
  • C3=4
  • C4=4
  • C5=4
  • C6=4
  • CIN=4
  • CLK=6
  • COUT=4
  • CQ=4
  • D1=2
  • D2=4
  • D3=4
  • D4=4
  • D5=4
  • D6=4
  • DQ=4
  • SR=6
SLICEM
  • A=19
  • A1=32
  • A2=32
  • A3=32
  • A4=32
  • A5=32
  • A6=32
  • AI=21
  • AMUX=5
  • AQ=4
  • AX=14
  • B=1
  • B1=14
  • B2=14
  • B3=14
  • B4=14
  • B5=14
  • B6=14
  • BI=3
  • BMUX=4
  • BQ=3
  • BX=11
  • C=2
  • C1=14
  • C2=14
  • C3=15
  • C4=15
  • C5=15
  • C6=14
  • CE=32
  • CI=3
  • CIN=2
  • CLK=32
  • CMUX=5
  • COUT=6
  • CQ=3
  • CX=12
  • D=1
  • D1=12
  • D2=12
  • D3=12
  • D4=12
  • D5=12
  • D6=12
  • DI=9
  • DMUX=28
  • DQ=2
  • DX=11
  • SR=1
SLICEX
  • A=17
  • A1=18
  • A2=21
  • A3=22
  • A4=25
  • A5=25
  • A6=25
  • AMUX=8
  • AQ=12
  • AX=2
  • B=7
  • B1=6
  • B2=7
  • B3=10
  • B4=11
  • B5=11
  • B6=12
  • BMUX=1
  • BQ=8
  • BX=2
  • C=8
  • C1=11
  • C2=13
  • C3=13
  • C4=13
  • C5=13
  • C6=13
  • CE=1
  • CLK=12
  • CMUX=2
  • CQ=7
  • CX=2
  • D=12
  • D1=5
  • D2=10
  • D3=10
  • D4=12
  • D5=13
  • D6=14
  • DMUX=3
  • DQ=4
  • DX=2
  • SR=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 6 5 0 0 0 0 0
bitgen 119 119 0 0 0 0 0
cse_server 55 55 0 0 0 0 0
map 121 119 0 0 0 0 0
ngcbuild 31 31 0 0 0 0 0
ngdbuild 128 128 0 0 0 0 0
par 119 119 0 0 0 0 0
trce 119 119 0 0 0 0 0
xst 238 236 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-03-11T11:18:09
PROP_intWbtProjectID=DA5799D64A8B44F68BD5C7E6F89F39D0 PROP_intWbtProjectIteration=14
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_xstPackIORegister=Yes
PROP_AutoTop=true PROP_DevFamily=Spartan6
PROP_DevDevice=xc6slx25 PROP_DevFamilyPMName=spartan6
PROP_DevPackage=ftg256 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-3 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=3
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=20.833 clkin2_period=20.833 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=4 primtype_sel=DCM_SP
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=true use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1 XST_NUM_ODDR2=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=49 NGDBUILD_NUM_FDCE=5
NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=2 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=26
NGDBUILD_NUM_LUT4=34 NGDBUILD_NUM_LUT5=22 NGDBUILD_NUM_LUT6=29 NGDBUILD_NUM_MUXCY=18
NGDBUILD_NUM_OBUF=9 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=20
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=49 NGDBUILD_NUM_FDCE=5
NGDBUILD_NUM_FDP=2 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=18 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=3 NGDBUILD_NUM_LUT2=4 NGDBUILD_NUM_LUT3=26 NGDBUILD_NUM_LUT4=34
NGDBUILD_NUM_LUT5=22 NGDBUILD_NUM_LUT6=29 NGDBUILD_NUM_MUXCY=18 NGDBUILD_NUM_OBUF=9
NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=20
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx25-3-ftg256
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=True
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5