# Static Timing Analysis

Project : | SysTimesr_PSoC5_Demo
Build Time : | 01/27/14 13:34:52
Device : | CY8C5868AXI-LP035
Temperature : | -40C - 85/125C
Vdda : | 5.00
Vddd : | 5.00
Vio0 : | 5.00
Vio1 : | 5.00
Vio2 : | 5.00
Vio3 : | 5.00
Voltage : | 5
Vusb : | 5.00

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 65.000 MHz | 65.000 MHz | N/A |
CyScBoostClk | CyMASTER_CLK | 9.286 MHz | 9.286 MHz | N/A |
CyBUS_CLK | CyMASTER_CLK | 65.000 MHz | 65.000 MHz | N/A |
CyPLL_OUT | CyPLL_OUT | 65.000 MHz | 65.000 MHz | N/A |