# Static Timing Analysis

Project : | SysTimers_PSoC4_Demo
Build Time : | 01/27/14 13:32:40
Device : | CY8C4245AXI-483
Temperature : | -40C - 85C
VDDA : | 3.30
VDDD : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyHFCLK | CyHFCLK | 24.000 MHz | 24.000 MHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 24.000 MHz | 24.000 MHz | N/A |
CyLFCLK | CyLFCLK | 32.000 kHz | 32.000 kHz | N/A |
CySYSCLK | CySYSCLK | 24.000 MHz | 24.000 MHz | N/A |