Static Timing Analysis

Project : tastierino_0
Build Time : 02/13/14 00:36:24
Device : CY8C5667AXI-LP006
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Async
Clock_RefreshAdc(routed) Clock_9
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_1_theACLK(fixed-function) ADC_SAR_1_theACLK(fixed-function) 1.600 MHz 1.600 MHz N/A
ADC_SAR_2_theACLK(fixed-function) ADC_SAR_2_theACLK(fixed-function) 1.600 MHz 1.600 MHz N/A
Clock_1(routed) Clock_1(routed) 100.000  Hz 100.000  Hz N/A
Clock_RefreshAdc(routed) Clock_RefreshAdc(routed) 10.000 kHz 10.000 kHz N/A
CyBUS_CLK(routed) CyBUS_CLK(routed) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 45.708 MHz
Clock_9 CyMASTER_CLK 12.000 MHz 12.000 MHz 40.579 MHz
ADC_SAR_1_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
ADC_SAR_2_theACLK CyMASTER_CLK 1.600 MHz 1.600 MHz N/A
Clock_RefreshAdc CyMASTER_CLK 10.000 kHz 10.000 kHz 45.708 MHz
Clock_1 CyMASTER_CLK 100.000  Hz 100.000  Hz 194.742 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 47.168 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_1040/q \Status_KeyBoard:sts:sts_reg\/status_0 194.742 MHz 5.135 36.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,4) 1 Net_1040 Net_1040/clock_0 Net_1040/q 1.250
Route 1 Net_1040 Net_1040/q \Status_KeyBoard:sts:sts_reg\/status_0 2.315
statuscell3 U(2,4) 1 \Status_KeyBoard:sts:sts_reg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 40.579 MHz 24.643 58.690
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.850
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:reload\/main_1 3.632
macrocell18 U(2,5) 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/main_1 \Counter_SocADC:CounterUDB:reload\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.291
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Counter_SocADC:CounterUDB:count_stored_i\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 40.659 MHz 24.595 58.738
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \Counter_SocADC:CounterUDB:count_stored_i\ \Counter_SocADC:CounterUDB:count_stored_i\/clock_0 \Counter_SocADC:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_SocADC:CounterUDB:count_stored_i\ \Counter_SocADC:CounterUDB:count_stored_i\/q \Counter_SocADC:CounterUDB:count_enable\/main_1 6.180
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_1 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 45.308 MHz 22.071 61.262
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell7 U(2,5) 1 \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \Counter_SocADC:CounterUDB:control_7\ \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SocADC:CounterUDB:count_enable\/main_0 2.326
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_0 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 52.843 MHz 18.924 64.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.850
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:status_3\/main_0 4.320
macrocell20 U(2,4) 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/main_0 \Counter_SocADC:CounterUDB:status_3\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 5.834
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_SocADC:CounterUDB:underflow_reg_i\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 69.915 MHz 14.303 69.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \Counter_SocADC:CounterUDB:underflow_reg_i\ \Counter_SocADC:CounterUDB:underflow_reg_i\/clock_0 \Counter_SocADC:CounterUDB:underflow_reg_i\/q 1.250
Route 1 \Counter_SocADC:CounterUDB:underflow_reg_i\ \Counter_SocADC:CounterUDB:underflow_reg_i\/q \Counter_SocADC:CounterUDB:status_3\/main_1 2.299
macrocell20 U(2,4) 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/main_1 \Counter_SocADC:CounterUDB:status_3\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 5.834
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
Net_887/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_0 75.844 MHz 13.185 70.148
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 Net_887 Net_887/clock_0 Net_887/q 1.250
Route 1 Net_887 Net_887/q \Counter_SocADC:CounterUDB:status_0\/main_1 4.076
macrocell19 U(2,4) 1 \Counter_SocADC:CounterUDB:status_0\ \Counter_SocADC:CounterUDB:status_0\/main_1 \Counter_SocADC:CounterUDB:status_0\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:status_0\ \Counter_SocADC:CounterUDB:status_0\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_0 2.939
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:underflow_reg_i\/main_0 85.675 MHz 11.672 71.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.850
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:underflow_reg_i\/main_0 4.312
macrocell21 U(2,4) 1 \Counter_SocADC:CounterUDB:underflow_reg_i\ SETUP 3.510
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_1 103.939 MHz 9.621 73.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.850
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_1 4.201
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_887/q cydff_1/ap_0 134.372 MHz 7.442 34.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 Net_887 Net_887/clock_0 Net_887/q 1.250
Route 1 Net_887 Net_887/q cydff_1/ap_0 6.192
macrocell22 U(2,5) 1 cydff_1 RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
cydff_2/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 45.708 MHz 21.878 19.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,5) 1 cydff_2 cydff_2/clock_0 cydff_2/q 1.250
Route 1 cydff_2 cydff_2/q \Counter_SocADC:CounterUDB:count_enable\/main_2 3.463
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_2 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
cydff_2/q \Counter_SocADC:CounterUDB:count_stored_i\/main_0 86.723 MHz 11.531 30.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,5) 1 cydff_2 cydff_2/clock_0 cydff_2/q 1.250
Route 1 cydff_2 cydff_2/q \Counter_SocADC:CounterUDB:count_stored_i\/main_0 6.771
macrocell17 U(1,5) 1 \Counter_SocADC:CounterUDB:count_stored_i\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 205.002 MHz 4.878 36.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell8 U(2,4) 1 \KeyPad_1:KbdControl:Sync:ctrl_reg\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/busclk \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 2.580
Route 1 \KeyPad_1:Net_116\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 2.298
macrocell1 U(2,4) 1 Net_1040 RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
cydff_1/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 47.168 MHz 21.201 20.466
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q \Counter_SocADC:CounterUDB:reload\/main_0 2.790
macrocell18 U(2,5) 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/main_0 \Counter_SocADC:CounterUDB:reload\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.291
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 245.459 MHz 4.074 37.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.824
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
cydff_1/q cydff_2/main_0 132.450 MHz 7.550 34.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q cydff_2/main_0 2.790
macrocell23 U(2,5) 1 cydff_2 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
DMA_Current/termout \Status_ADC_CURRENT:sts:sts_reg\/status_0 51.962 MHz 19.245 22.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqHod=(0)][DrqId=(0)] 1 DMA_Current DMA_Current/clock DMA_Current/termout 9.000
Route 1 Net_621 DMA_Current/termout \Status_ADC_CURRENT:sts:sts_reg\/status_0 8.675
statuscell1 U(1,1) 1 \Status_ADC_CURRENT:sts:sts_reg\ SETUP 1.570
Clock Skew 0.000
DMA_Therm/termout \Status_ADC_TEMP:sts:sts_reg\/status_0 63.520 MHz 15.743 25.924
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell2 [DrqHod=(0)][DrqId=(1)] 1 DMA_Therm DMA_Therm/clock DMA_Therm/termout 9.000
Route 1 Net_709 DMA_Therm/termout \Status_ADC_TEMP:sts:sts_reg\/status_0 5.173
statuscell2 U(3,4) 1 \Status_ADC_TEMP:sts:sts_reg\ SETUP 1.570
Clock Skew 0.000
I_SCK(0)/fb Net_595_0/clk_en 91.491 MHz 10.930 30.737
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_0/clk_en 6.885
macrocell3 U(3,5) 1 Net_595_0 SETUP 2.100
Clock Skew 0.000
I_SDO(0)/fb Net_595_0/main_0 95.703 MHz 10.449 31.218
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell14 P4[4] 1 I_SDO(0) I_SDO(0)/in_clock I_SDO(0)/fb 1.800
Route 1 Net_479 I_SDO(0)/fb Net_595_0/main_0 5.139
macrocell3 U(3,5) 1 Net_595_0 SETUP 3.510
Clock Skew 0.000
I_SCK(0)/fb Net_595_3/clk_en 97.838 MHz 10.221 31.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_3/clk_en 6.176
macrocell6 U(3,3) 1 Net_595_3 SETUP 2.100
Clock Skew 0.000
I_SCK(0)/fb Net_595_4/clk_en 97.838 MHz 10.221 31.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_4/clk_en 6.176
macrocell7 U(3,3) 1 Net_595_4 SETUP 2.100
Clock Skew 0.000
I_SCK(0)/fb Net_595_5/clk_en 97.838 MHz 10.221 31.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_5/clk_en 6.176
macrocell8 U(3,3) 1 Net_595_5 SETUP 2.100
Clock Skew 0.000
I_SCK(0)/fb Net_595_6/clk_en 97.838 MHz 10.221 31.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_6/clk_en 6.176
macrocell9 U(3,3) 1 Net_595_6 SETUP 2.100
Clock Skew 0.000
I_SCK(0)/fb Net_595_7/clk_en 97.838 MHz 10.221 31.446
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_7/clk_en 6.176
macrocell10 U(3,3) 1 Net_595_7 SETUP 2.100
Clock Skew 0.000
Net_595_3/q Net_595_4/main_0 106.045 MHz 9.430 32.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,3) 1 Net_595_3 Net_595_3/clock_0 Net_595_3/q 1.250
Route 1 Net_595_3 Net_595_3/q Net_595_4/main_0 4.670
macrocell7 U(3,3) 1 Net_595_4 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_1040/q \Status_KeyBoard:sts:sts_reg\/status_0 1.565
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,4) 1 Net_1040 Net_1040/clock_0 Net_1040/q 1.250
Route 1 Net_1040 Net_1040/q \Status_KeyBoard:sts:sts_reg\/status_0 2.315
statuscell3 U(2,4) 1 \Status_KeyBoard:sts:sts_reg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_1 5.471
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.270
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_1 4.201
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:underflow_reg_i\/main_0 7.582
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.270
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:underflow_reg_i\/main_0 4.312
macrocell21 U(2,4) 1 \Counter_SocADC:CounterUDB:underflow_reg_i\ HOLD 0.000
Clock Skew 0.000
Net_887/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_0 9.615
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 Net_887 Net_887/clock_0 Net_887/q 1.250
Route 1 Net_887 Net_887/q \Counter_SocADC:CounterUDB:status_0\/main_1 4.076
macrocell19 U(2,4) 1 \Counter_SocADC:CounterUDB:status_0\ \Counter_SocADC:CounterUDB:status_0\/main_1 \Counter_SocADC:CounterUDB:status_0\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:status_0\ \Counter_SocADC:CounterUDB:status_0\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_0 2.939
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 10.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell7 U(2,5) 1 \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\ \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \Counter_SocADC:CounterUDB:control_7\ \Counter_SocADC:CounterUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \Counter_SocADC:CounterUDB:count_enable\/main_0 2.326
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_0 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Counter_SocADC:CounterUDB:underflow_reg_i\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 10.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,4) 1 \Counter_SocADC:CounterUDB:underflow_reg_i\ \Counter_SocADC:CounterUDB:underflow_reg_i\/clock_0 \Counter_SocADC:CounterUDB:underflow_reg_i\/q 1.250
Route 1 \Counter_SocADC:CounterUDB:underflow_reg_i\ \Counter_SocADC:CounterUDB:underflow_reg_i\/q \Counter_SocADC:CounterUDB:status_3\/main_1 2.299
macrocell20 U(2,4) 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/main_1 \Counter_SocADC:CounterUDB:status_3\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 5.834
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 12.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.270
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:reload\/main_1 3.632
macrocell18 U(2,5) 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/main_1 \Counter_SocADC:CounterUDB:reload\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.291
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Counter_SocADC:CounterUDB:count_stored_i\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 13.075
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \Counter_SocADC:CounterUDB:count_stored_i\ \Counter_SocADC:CounterUDB:count_stored_i\/clock_0 \Counter_SocADC:CounterUDB:count_stored_i\/q 1.250
Route 1 \Counter_SocADC:CounterUDB:count_stored_i\ \Counter_SocADC:CounterUDB:count_stored_i\/q \Counter_SocADC:CounterUDB:count_enable\/main_1 6.180
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_1 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
\Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 14.774
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/clock \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb 3.270
Route 1 \Counter_SocADC:CounterUDB:status_1\ \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/z0_comb \Counter_SocADC:CounterUDB:status_3\/main_0 4.320
macrocell20 U(2,4) 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/main_0 \Counter_SocADC:CounterUDB:status_3\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:status_3\ \Counter_SocADC:CounterUDB:status_3\/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/status_3 5.834
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_887/q cydff_1/ap_0 7.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 Net_887 Net_887/clock_0 Net_887/q 1.250
Route 1 Net_887 Net_887/q cydff_1/ap_0 6.192
macrocell22 U(2,5) 1 cydff_1 REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
cydff_2/q \Counter_SocADC:CounterUDB:count_stored_i\/main_0 49.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,5) 1 cydff_2 cydff_2/clock_0 cydff_2/q 1.250
Route 1 cydff_2 cydff_2/q \Counter_SocADC:CounterUDB:count_stored_i\/main_0 6.771
macrocell17 U(1,5) 1 \Counter_SocADC:CounterUDB:count_stored_i\ HOLD 0.000
Clock Skew 0.000
cydff_2/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 52.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(2,5) 1 cydff_2 cydff_2/clock_0 cydff_2/q 1.250
Route 1 cydff_2 cydff_2/q \Counter_SocADC:CounterUDB:count_enable\/main_2 3.463
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_2 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell8 U(2,4) 1 \KeyPad_1:KbdControl:Sync:ctrl_reg\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/busclk \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 2.040
Route 1 \KeyPad_1:Net_116\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 2.298
macrocell1 U(2,4) 1 Net_1040 REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.074
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.824
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000
cydff_1/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 9.681
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q \Counter_SocADC:CounterUDB:reload\/main_0 2.790
macrocell18 U(2,5) 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/main_0 \Counter_SocADC:CounterUDB:reload\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:reload\ \Counter_SocADC:CounterUDB:reload\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_0 2.291
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
cydff_1/q cydff_2/main_0 4.040
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q cydff_2/main_0 2.790
macrocell23 U(2,5) 1 cydff_2 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_595_1/q Net_595_2/main_0 3.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,4) 1 Net_595_1 Net_595_1/clock_0 Net_595_1/q 1.250
Route 1 Net_595_1 Net_595_1/q Net_595_2/main_0 2.284
macrocell5 U(3,4) 1 Net_595_2 HOLD 0.000
Clock Skew 0.000
Net_595_6/q Net_595_7/main_0 4.032
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,3) 1 Net_595_6 Net_595_6/clock_0 Net_595_6/q 1.250
Route 1 Net_595_6 Net_595_6/q Net_595_7/main_0 2.782
macrocell10 U(3,3) 1 Net_595_7 HOLD 0.000
Clock Skew 0.000
Net_595_0/q Net_595_1/main_0 4.172
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(3,5) 1 Net_595_0 Net_595_0/clock_0 Net_595_0/q 1.250
Route 1 Net_595_0 Net_595_0/q Net_595_1/main_0 2.922
macrocell4 U(3,4) 1 Net_595_1 HOLD 0.000
Clock Skew 0.000
Net_595_2/q Net_595_3/main_0 4.322
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 Net_595_2 Net_595_2/clock_0 Net_595_2/q 1.250
Route 1 Net_595_2 Net_595_2/q Net_595_3/main_0 3.072
macrocell6 U(3,3) 1 Net_595_3 HOLD 0.000
Clock Skew 0.000
\Control_ADC:Sync:ctrl_reg\/control_0 cydff_1/clk_en 4.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,5) 1 \Control_ADC:Sync:ctrl_reg\ \Control_ADC:Sync:ctrl_reg\/busclk \Control_ADC:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_886 \Control_ADC:Sync:ctrl_reg\/control_0 cydff_1/clk_en 2.301
macrocell22 U(2,5) 1 cydff_1 HOLD 0.000
Clock Skew 0.000
Net_595_5/q Net_595_6/main_0 4.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(3,3) 1 Net_595_5 Net_595_5/clock_0 Net_595_5/q 1.250
Route 1 Net_595_5 Net_595_5/q Net_595_6/main_0 3.589
macrocell9 U(3,3) 1 Net_595_6 HOLD 0.000
Clock Skew 0.000
Net_595_4/q Net_595_5/main_0 5.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,3) 1 Net_595_4 Net_595_4/clock_0 Net_595_4/q 1.250
Route 1 Net_595_4 Net_595_4/q Net_595_5/main_0 4.640
macrocell8 U(3,3) 1 Net_595_5 HOLD 0.000
Clock Skew 0.000
Net_595_3/q Net_595_4/main_0 5.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,3) 1 Net_595_3 Net_595_3/clock_0 Net_595_3/q 1.250
Route 1 Net_595_3 Net_595_3/q Net_595_4/main_0 4.670
macrocell7 U(3,3) 1 Net_595_4 HOLD 0.000
Clock Skew 0.000
I_SDO(0)/fb Net_595_0/main_0 6.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell14 P4[4] 1 I_SDO(0) I_SDO(0)/in_clock I_SDO(0)/fb 1.800
Route 1 Net_479 I_SDO(0)/fb Net_595_0/main_0 5.139
macrocell3 U(3,5) 1 Net_595_0 HOLD 0.000
Clock Skew 0.000
I_SCK(0)/fb Net_595_1/clk_en 7.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell13 P4[5] 1 I_SCK(0) I_SCK(0)/in_clock I_SCK(0)/fb 1.945
Route 1 Net_480 I_SCK(0)/fb Net_595_1/clk_en 5.269
macrocell4 U(3,4) 1 Net_595_1 HOLD 0.000
Clock Skew 0.000
+ Asynchronous Clock Crossing Section
+ Source Clock Clock_RefreshAdc(routed)
Source Destination Delay (ns)
ClockBlock/dclk_1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 25.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_1 0.000
Route 1 Net_929_local ClockBlock/dclk_1 \Counter_SocADC:CounterUDB:count_enable\/main_3 8.147
macrocell16 U(2,5) 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/main_3 \Counter_SocADC:CounterUDB:count_enable\/q 3.350
Route 1 \Counter_SocADC:CounterUDB:count_enable\ \Counter_SocADC:CounterUDB:count_enable\/q \Counter_SocADC:CounterUDB:sC8:counterdp:u0\/cs_addr_1 2.295
datapathcell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sC8:counterdp:u0\ SETUP 11.520
Clock Skew 0.000
ClockBlock/dclk_1 \Counter_SocADC:CounterUDB:count_stored_i\/main_1 14.891
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_1 0.000
Route 1 Net_929_local ClockBlock/dclk_1 \Counter_SocADC:CounterUDB:count_stored_i\/main_1 11.381
macrocell17 U(1,5) 1 \Counter_SocADC:CounterUDB:count_stored_i\ SETUP 3.510
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_ENA_POWER:Sync:ctrl_reg\/control_0 PWR2(0)_PAD 30.530
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Control_ENA_POWER:Sync:ctrl_reg\ \Control_ENA_POWER:Sync:ctrl_reg\/busclk \Control_ENA_POWER:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_628 \Control_ENA_POWER:Sync:ctrl_reg\/control_0 Net_632/main_1 2.621
macrocell12 U(0,5) 1 Net_632 Net_632/main_1 Net_632/q 3.350
Route 1 Net_632 Net_632/q PWR2(0)/pin_input 6.323
iocell29 P6[4] 1 PWR2(0) PWR2(0)/pin_input PWR2(0)/pad_out 15.656
Route 1 PWR2(0)_PAD PWR2(0)/pad_out PWR2(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_ENA_POWER:Sync:ctrl_reg\/control_0 PWR4(0)_PAD 29.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Control_ENA_POWER:Sync:ctrl_reg\ \Control_ENA_POWER:Sync:ctrl_reg\/busclk \Control_ENA_POWER:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_628 \Control_ENA_POWER:Sync:ctrl_reg\/control_0 Net_539/main_1 2.635
macrocell2 U(0,5) 1 Net_539 Net_539/main_1 Net_539/q 3.350
Route 1 Net_539 Net_539/q PWR4(0)/pin_input 5.487
iocell31 P6[6] 1 PWR4(0) PWR4(0)/pin_input PWR4(0)/pad_out 15.726
Route 1 PWR4(0)_PAD PWR4(0)/pad_out PWR4(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_ENA_POWER:Sync:ctrl_reg\/control_0 PWR5(0)_PAD 29.535
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Control_ENA_POWER:Sync:ctrl_reg\ \Control_ENA_POWER:Sync:ctrl_reg\/busclk \Control_ENA_POWER:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_628 \Control_ENA_POWER:Sync:ctrl_reg\/control_0 Net_644/main_1 2.635
macrocell14 U(0,5) 1 Net_644 Net_644/main_1 Net_644/q 3.350
Route 1 Net_644 Net_644/q PWR5(0)/pin_input 6.366
iocell32 P6[7] 1 PWR5(0) PWR5(0)/pin_input PWR5(0)/pad_out 14.604
Route 1 PWR5(0)_PAD PWR5(0)/pad_out PWR5(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_ENA_POWER:Sync:ctrl_reg\/control_0 PWR3(0)_PAD 29.394
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Control_ENA_POWER:Sync:ctrl_reg\ \Control_ENA_POWER:Sync:ctrl_reg\/busclk \Control_ENA_POWER:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_628 \Control_ENA_POWER:Sync:ctrl_reg\/control_0 Net_636/main_1 2.621
macrocell13 U(0,5) 1 Net_636 Net_636/main_1 Net_636/q 3.350
Route 1 Net_636 Net_636/q PWR3(0)/pin_input 6.333
iocell30 P6[5] 1 PWR3(0) PWR3(0)/pin_input PWR3(0)/pad_out 14.510
Route 1 PWR3(0)_PAD PWR3(0)/pad_out PWR3(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_ENA_POWER:Sync:ctrl_reg\/control_0 PWR1(0)_PAD 29.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,5) 1 \Control_ENA_POWER:Sync:ctrl_reg\ \Control_ENA_POWER:Sync:ctrl_reg\/busclk \Control_ENA_POWER:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_628 \Control_ENA_POWER:Sync:ctrl_reg\/control_0 Net_629/main_1 2.635
macrocell11 U(0,5) 1 Net_629 Net_629/main_1 Net_629/q 3.350
Route 1 Net_629 Net_629/q PWR1(0)/pin_input 5.814
iocell28 P2[7] 1 PWR1(0) PWR1(0)/pin_input PWR1(0)/pad_out 14.874
Route 1 PWR1(0)_PAD PWR1(0)/pad_out PWR1(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_LAMP:Sync:ctrl_reg\/control_2 LAMP_B(0)_PAD 28.165
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(1,1) 1 \Control_LAMP:Sync:ctrl_reg\ \Control_LAMP:Sync:ctrl_reg\/busclk \Control_LAMP:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_368 \Control_LAMP:Sync:ctrl_reg\/control_2 LAMP_B(0)/pin_input 6.456
iocell17 P15[6] 1 LAMP_B(0) LAMP_B(0)/pin_input LAMP_B(0)/pad_out 19.129
Route 1 LAMP_B(0)_PAD LAMP_B(0)/pad_out LAMP_B(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_LAMP:Sync:ctrl_reg\/control_1 LAMP_G(0)_PAD 28.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(1,1) 1 \Control_LAMP:Sync:ctrl_reg\ \Control_LAMP:Sync:ctrl_reg\/busclk \Control_LAMP:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_367 \Control_LAMP:Sync:ctrl_reg\/control_1 LAMP_G(0)/pin_input 6.436
iocell18 P15[7] 1 LAMP_G(0) LAMP_G(0)/pin_input LAMP_G(0)/pad_out 19.053
Route 1 LAMP_G(0)_PAD LAMP_G(0)/pad_out LAMP_G(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_KEY:Sync:ctrl_reg\/control_0 KIN1(0)_PAD 25.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \Control_KEY:Sync:ctrl_reg\ \Control_KEY:Sync:ctrl_reg\/busclk \Control_KEY:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_426 \Control_KEY:Sync:ctrl_reg\/control_0 KIN1(0)/pin_input 7.112
iocell15 P15[4] 1 KIN1(0) KIN1(0)/pin_input KIN1(0)/pad_out 15.848
Route 1 KIN1(0)_PAD KIN1(0)/pad_out KIN1(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_KEY:Sync:ctrl_reg\/control_1 KIN2(0)_PAD 25.498
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,3) 1 \Control_KEY:Sync:ctrl_reg\ \Control_KEY:Sync:ctrl_reg\/busclk \Control_KEY:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_423 \Control_KEY:Sync:ctrl_reg\/control_1 KIN2(0)/pin_input 6.993
iocell16 P15[5] 1 KIN2(0) KIN2(0)/pin_input KIN2(0)/pad_out 15.925
Route 1 KIN2(0)_PAD KIN2(0)/pad_out KIN2(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_US:Sync:ctrl_reg\/control_0 EXT(0)_PAD 24.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Control_US:Sync:ctrl_reg\ \Control_US:Sync:ctrl_reg\/busclk \Control_US:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_391 \Control_US:Sync:ctrl_reg\/control_0 EXT(0)/pin_input 6.317
iocell7 P1[7] 1 EXT(0) EXT(0)/pin_input EXT(0)/pad_out 15.381
Route 1 EXT(0)_PAD EXT(0)/pad_out EXT(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_US:Sync:ctrl_reg\/control_3 BIT0(0)_PAD 24.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Control_US:Sync:ctrl_reg\ \Control_US:Sync:ctrl_reg\/busclk \Control_US:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_390 \Control_US:Sync:ctrl_reg\/control_3 BIT0(0)/pin_input 6.452
iocell3 P1[3] 1 BIT0(0) BIT0(0)/pin_input BIT0(0)/pad_out 15.111
Route 1 BIT0(0)_PAD BIT0(0)/pad_out BIT0(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_LAMP:Sync:ctrl_reg\/control_3 ENA_LAMP(0)_PAD 23.863
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(1,1) 1 \Control_LAMP:Sync:ctrl_reg\ \Control_LAMP:Sync:ctrl_reg\/busclk \Control_LAMP:Sync:ctrl_reg\/control_3 2.580
Route 1 Net_369 \Control_LAMP:Sync:ctrl_reg\/control_3 ENA_LAMP(0)/pin_input 6.499
iocell6 P5[7] 1 ENA_LAMP(0) ENA_LAMP(0)/pin_input ENA_LAMP(0)/pad_out 14.784
Route 1 ENA_LAMP(0)_PAD ENA_LAMP(0)/pad_out ENA_LAMP(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_LAMP:Sync:ctrl_reg\/control_0 LAMP_R(0)_PAD 23.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell4 U(1,1) 1 \Control_LAMP:Sync:ctrl_reg\ \Control_LAMP:Sync:ctrl_reg\/busclk \Control_LAMP:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_370 \Control_LAMP:Sync:ctrl_reg\/control_0 LAMP_R(0)/pin_input 7.005
iocell19 P15[0] 1 LAMP_R(0) LAMP_R(0)/pin_input LAMP_R(0)/pad_out 14.255
Route 1 LAMP_R(0)_PAD LAMP_R(0)/pad_out LAMP_R(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_US:Sync:ctrl_reg\/control_4 BIT1(0)_PAD 23.729
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Control_US:Sync:ctrl_reg\ \Control_US:Sync:ctrl_reg\/busclk \Control_US:Sync:ctrl_reg\/control_4 2.580
Route 1 Net_392 \Control_US:Sync:ctrl_reg\/control_4 BIT1(0)/pin_input 5.471
iocell4 P1[4] 1 BIT1(0) BIT1(0)/pin_input BIT1(0)/pad_out 15.678
Route 1 BIT1(0)_PAD BIT1(0)/pad_out BIT1(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_US:Sync:ctrl_reg\/control_1 I_DEGASS(0)_PAD 23.616
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Control_US:Sync:ctrl_reg\ \Control_US:Sync:ctrl_reg\/busclk \Control_US:Sync:ctrl_reg\/control_1 2.580
Route 1 Net_388 \Control_US:Sync:ctrl_reg\/control_1 I_DEGASS(0)/pin_input 5.566
iocell11 P1[2] 1 I_DEGASS(0) I_DEGASS(0)/pin_input I_DEGASS(0)/pad_out 15.470
Route 1 I_DEGASS(0)_PAD I_DEGASS(0)/pad_out I_DEGASS(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_US:Sync:ctrl_reg\/control_5 BIT2(0)_PAD 23.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Control_US:Sync:ctrl_reg\ \Control_US:Sync:ctrl_reg\/busclk \Control_US:Sync:ctrl_reg\/control_5 2.580
Route 1 Net_398 \Control_US:Sync:ctrl_reg\/control_5 BIT2(0)/pin_input 5.481
iocell5 P1[5] 1 BIT2(0) BIT2(0)/pin_input BIT2(0)/pad_out 15.342
Route 1 BIT2(0)_PAD BIT2(0)/pad_out BIT2(0)_PAD 0.000
Clock Clock path delay 0.000
\Control_US:Sync:ctrl_reg\/control_2 I_PULSE(0)_PAD 23.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(0,1) 1 \Control_US:Sync:ctrl_reg\ \Control_US:Sync:ctrl_reg\/busclk \Control_US:Sync:ctrl_reg\/control_2 2.580
Route 1 Net_389 \Control_US:Sync:ctrl_reg\/control_2 I_PULSE(0)/pin_input 5.574
iocell12 P1[6] 1 I_PULSE(0) I_PULSE(0)/pin_input I_PULSE(0)/pad_out 15.071
Route 1 I_PULSE(0)_PAD I_PULSE(0)/pad_out I_PULSE(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_887/q cydff_1/ap_0 134.372 MHz 7.442 34.225
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 Net_887 Net_887/clock_0 Net_887/q 1.250
Route 1 Net_887 Net_887/q cydff_1/ap_0 6.192
macrocell22 U(2,5) 1 cydff_1 RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 205.002 MHz 4.878 36.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell8 U(2,4) 1 \KeyPad_1:KbdControl:Sync:ctrl_reg\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/busclk \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 2.580
Route 1 \KeyPad_1:Net_116\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 2.298
macrocell1 U(2,4) 1 Net_1040 RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 245.459 MHz 4.074 37.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.824
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
Net_887/q cydff_1/ap_0 7.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 Net_887 Net_887/clock_0 Net_887/q 1.250
Route 1 Net_887 Net_887/q cydff_1/ap_0 6.192
macrocell22 U(2,5) 1 cydff_1 REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 4.338
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell8 U(2,4) 1 \KeyPad_1:KbdControl:Sync:ctrl_reg\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/busclk \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 2.040
Route 1 \KeyPad_1:Net_116\ \KeyPad_1:KbdControl:Sync:ctrl_reg\/control_0 Net_1040/ap_0 2.298
macrocell1 U(2,4) 1 Net_1040 REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 4.074
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(2,5) 1 cydff_1 cydff_1/clock_0 cydff_1/q 1.250
Route 1 cydff_1 cydff_1/q \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\/reset 2.824
statusicell1 U(2,5) 1 \Counter_SocADC:CounterUDB:sSTSReg:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000