Static Timing Analysis

Project : OwlEars2
Build Time : 10/05/14 16:23:45
Device : CY8C5868LTI-LP039
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_Seq_IntClock(routed) ADC_SAR_Seq_IntClock(routed) 2.182 MHz 2.182 MHz N/A
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_SAR_Seq_IntClock CyMASTER_CLK 2.182 MHz 2.182 MHz 28.559 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 53.242 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 458.333ns(2.18182 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_34\/main_0 28.559 MHz 35.015 423.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_34\/main_0 12.630
macrocell37 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_34\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_53\/main_0 28.559 MHz 35.015 423.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_53\/main_0 12.630
macrocell58 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_53\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_38\/main_0 28.573 MHz 34.998 423.335
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_38\/main_0 12.613
macrocell41 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_38\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_32\/main_0 29.026 MHz 34.452 423.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_32\/main_0 12.067
macrocell35 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_32\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_47\/main_0 29.026 MHz 34.452 423.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_47\/main_0 12.067
macrocell51 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_47\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_51\/main_0 29.026 MHz 34.452 423.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_51\/main_0 12.067
macrocell56 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_51\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_56\/main_0 29.716 MHz 33.652 424.681
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_56\/main_0 11.267
macrocell61 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_56\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_28\/main_0 30.348 MHz 32.951 425.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_28\/main_0 10.566
macrocell30 U(2,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_28\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_48\/main_0 30.348 MHz 32.951 425.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_48\/main_0 10.566
macrocell52 U(2,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_48\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_57\/main_0 30.348 MHz 32.951 425.382
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_2\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 8.633
macrocell3 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_6 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.292
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_57\/main_0 10.566
macrocell62 U(2,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_57\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 135.962 MHz 7.355 34.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,3) 1 Net_954 Net_954/clock_0 Net_954/q 1.250
Route 1 Net_954 Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 2.595
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 53.282 MHz 18.768 22.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 6.258
macrocell1 U(3,3) 1 Net_954 SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_0 135.999 MHz 7.353 34.314
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_0 2.593
macrocell1 U(3,3) 1 Net_954 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 53.242 MHz 18.782 22.885
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 6.272
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 136.110 MHz 7.347 34.320
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 2.587
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_954/q Net_954/main_1 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,3) 1 Net_954 Net_954/clock_0 Net_954/q 1.250
macrocell1 U(3,3) 1 Net_954 Net_954/q Net_954/main_1 2.595
macrocell1 U(3,3) 1 Net_954 HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_11\/main_6 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_11\/main_6 3.098
macrocell12 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_11\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_24\/main_6 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_24\/main_6 3.098
macrocell26 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_24\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_44\/main_6 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_44\/main_6 3.098
macrocell48 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_44\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_61\/main_6 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_61\/main_6 3.098
macrocell67 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_61\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_12\/main_6 4.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_12\/main_6 3.099
macrocell13 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_12\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_20\/main_6 4.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_20\/main_6 3.099
macrocell22 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_20\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_43\/main_6 4.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_43\/main_6 3.099
macrocell47 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_43\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_54\/main_6 4.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_0\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_54\/main_6 3.099
macrocell59 U(2,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_54\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_30\/main_3 4.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,0) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_3\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_3\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_3\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_3\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_30\/main_3 3.158
macrocell33 U(2,0) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_30\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 3.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,3) 1 Net_954 Net_954/clock_0 Net_954/q 1.250
Route 1 Net_954 Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 2.595
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_0 3.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_0 2.593
macrocell1 U(3,3) 1 Net_954 HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 15.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 6.258
macrocell1 U(3,3) 1 Net_954 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 3.837
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 2.587
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 15.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 6.272
macrocell74 U(3,3) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2C_M:I2C_FF\/sda_out SDA_1(0)_PAD:out 26.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_M:I2C_FF\ \I2C_M:I2C_FF\/clock \I2C_M:I2C_FF\/sda_out 1.000
Route 1 \I2C_M:sda_x_wire\ \I2C_M:I2C_FF\/sda_out SDA_1(0)/pin_input 9.470
iocell9 P0[1] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 15.802
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_M:I2C_FF\/scl_out SCL_1(0)_PAD:out 25.302
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_M:I2C_FF\ \I2C_M:I2C_FF\/clock \I2C_M:I2C_FF\/scl_out 1.000
Route 1 \I2C_M:Net_643_0\ \I2C_M:I2C_FF\/scl_out SCL_1(0)/pin_input 9.051
iocell8 P0[0] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 15.251
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000