# Static Timing Analysis

Project : | Design02
Build Time : | 05/03/20 18:02:41
Device : | CYBLE-416045-02
Temperature : | -40C
VBACKUP : | 3.30
VDDA : | 3.30
VDDA_CSD : | 3.30
VDDD : | 3.30
VDDIO_0 : | 3.30
VDDIO_0_RCV : | 3.30
VDDIO_1 : | 3.30
VDDIO_A : | 3.30
VDDQ : | 3.30
VDD_NS : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyClk_Fast | CyClk_Fast | 100.000 MHz | 100.000 MHz | N/A |
CyClk_HF0 | CyClk_HF0 | 100.000 MHz | 100.000 MHz | N/A |
CyClk_LF | CyClk_LF | 32.000 kHz | 32.000 kHz | N/A |
CyClk_Peri | CyClk_Peri | 50.000 MHz | 50.000 MHz | N/A |
CyClk_Slow | CyClk_Peri | 50.000 MHz | 50.000 MHz | N/A |
CyFLL | CyFLL | 100.000 MHz | 100.000 MHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 8.000 MHz | 8.000 MHz | N/A |
CyPeriClk_App | CyPeriClk_App | 50.000 MHz | 50.000 MHz | N/A |