Static Timing Analysis

Project : TestBench
Build Time : 10/10/12 15:06:14
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
LED_PWM_Clock CyMASTER_CLK 250.000 kHz 250.000 kHz 50.736 MHz
LED_Refresh_Clock CyMASTER_CLK 500.000  Hz 500.000  Hz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
LED_Refresh_Clock(routed) LED_Refresh_Clock(routed) 500.000  Hz 500.000  Hz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 4000ns(250 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 50.736 MHz 19.710 3980.290
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.340
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:runmode_enable\/q \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 66.405 MHz 15.059 3984.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(3,4) 1 \LED:COM_PWM:PWMUDB:runmode_enable\ \LED:COM_PWM:PWMUDB:runmode_enable\/clock_0 \LED:COM_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:runmode_enable\ \LED:COM_PWM:PWMUDB:runmode_enable\/q \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.289
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:Brightness\/main_1 86.957 MHz 11.500 3988.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \LED:COM_PWM:PWMUDB:compare1\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:Brightness\/main_1 2.310
macrocell5 U(3,4) 1 \LED:Brightness\ SETUP 3.510
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:prevCompare1\/main_0 86.957 MHz 11.500 3988.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \LED:COM_PWM:PWMUDB:compare1\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:prevCompare1\/main_0 2.310
macrocell7 U(3,4) 1 \LED:COM_PWM:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:status_0\/main_0 86.957 MHz 11.500 3988.500
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \LED:COM_PWM:PWMUDB:compare1\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:status_0\/main_0 2.310
macrocell9 U(3,4) 1 \LED:COM_PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 89.318 MHz 11.196 3988.804
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
Route 1 \LED:COM_PWM:PWMUDB:tc_i\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 5.776
statusicell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:final_kill_reg\/q \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 92.670 MHz 10.791 3989.209
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,4) 1 \LED:COM_PWM:PWMUDB:final_kill_reg\ \LED:COM_PWM:PWMUDB:final_kill_reg\/clock_0 \LED:COM_PWM:PWMUDB:final_kill_reg\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:final_kill_reg\ \LED:COM_PWM:PWMUDB:final_kill_reg\/q \LED:COM_PWM:PWMUDB:status_5\/main_0 2.295
macrocell10 U(2,4) 1 \LED:COM_PWM:PWMUDB:status_5\ \LED:COM_PWM:PWMUDB:status_5\/main_0 \LED:COM_PWM:PWMUDB:status_5\/q 3.350
Route 1 \LED:COM_PWM:PWMUDB:status_5\ \LED:COM_PWM:PWMUDB:status_5\/q \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 2.326
statusicell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\ SETUP 1.570
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:COM_PWM:PWMUDB:runmode_enable\/main_0 112.246 MHz 8.909 3991.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \LED:COM_PWM:PWMUDB:ctrl_enable\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:COM_PWM:PWMUDB:runmode_enable\/main_0 2.819
macrocell8 U(3,4) 1 \LED:COM_PWM:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:Brightness\/main_0 112.360 MHz 8.900 3991.100
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.580
Route 1 \LED:COM_PWM:PWMUDB:ctrl_enable\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:Brightness\/main_0 2.810
macrocell5 U(3,4) 1 \LED:Brightness\ SETUP 3.510
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:prevCompare1\/q \LED:COM_PWM:PWMUDB:status_0\/main_1 141.764 MHz 7.054 3992.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,4) 1 \LED:COM_PWM:PWMUDB:prevCompare1\ \LED:COM_PWM:PWMUDB:prevCompare1\/clock_0 \LED:COM_PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:prevCompare1\ \LED:COM_PWM:PWMUDB:prevCompare1\/q \LED:COM_PWM:PWMUDB:status_0\/main_1 2.294
macrocell9 U(3,4) 1 \LED:COM_PWM:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\LED:COM_PWM:PWMUDB:status_0\/q \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 1.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,4) 1 \LED:COM_PWM:PWMUDB:status_0\ \LED:COM_PWM:PWMUDB:status_0\/clock_0 \LED:COM_PWM:PWMUDB:status_0\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:status_0\ \LED:COM_PWM:PWMUDB:status_0\/q \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_0 2.311
statusicell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:runmode_enable\/q \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(3,4) 1 \LED:COM_PWM:PWMUDB:runmode_enable\ \LED:COM_PWM:PWMUDB:runmode_enable\/clock_0 \LED:COM_PWM:PWMUDB:runmode_enable\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:runmode_enable\ \LED:COM_PWM:PWMUDB:runmode_enable\/q \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.289
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:prevCompare1\/q \LED:COM_PWM:PWMUDB:status_0\/main_1 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(3,4) 1 \LED:COM_PWM:PWMUDB:prevCompare1\ \LED:COM_PWM:PWMUDB:prevCompare1\/clock_0 \LED:COM_PWM:PWMUDB:prevCompare1\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:prevCompare1\ \LED:COM_PWM:PWMUDB:prevCompare1\/q \LED:COM_PWM:PWMUDB:status_0\/main_1 2.294
macrocell9 U(3,4) 1 \LED:COM_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:Brightness\/main_0 4.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \LED:COM_PWM:PWMUDB:ctrl_enable\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:Brightness\/main_0 2.810
macrocell5 U(3,4) 1 \LED:Brightness\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:COM_PWM:PWMUDB:runmode_enable\/main_0 4.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 2.040
Route 1 \LED:COM_PWM:PWMUDB:ctrl_enable\ \LED:COM_PWM:PWMUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \LED:COM_PWM:PWMUDB:runmode_enable\/main_0 2.819
macrocell8 U(3,4) 1 \LED:COM_PWM:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:Brightness\/main_1 5.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \LED:COM_PWM:PWMUDB:compare1\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:Brightness\/main_1 2.310
macrocell5 U(3,4) 1 \LED:Brightness\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:prevCompare1\/main_0 5.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \LED:COM_PWM:PWMUDB:compare1\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:prevCompare1\/main_0 2.310
macrocell7 U(3,4) 1 \LED:COM_PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:status_0\/main_0 5.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \LED:COM_PWM:PWMUDB:compare1\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/cl0_comb \LED:COM_PWM:PWMUDB:status_0\/main_0 2.310
macrocell9 U(3,4) 1 \LED:COM_PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 7.046
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/clock \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.270
Route 1 \LED:COM_PWM:PWMUDB:tc_i\ \LED:COM_PWM:PWMUDB:sP8:pwmdp:u0\/z0_comb \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_2 5.776
statusicell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
\LED:COM_PWM:PWMUDB:final_kill_reg\/q \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 7.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,4) 1 \LED:COM_PWM:PWMUDB:final_kill_reg\ \LED:COM_PWM:PWMUDB:final_kill_reg\/clock_0 \LED:COM_PWM:PWMUDB:final_kill_reg\/q 1.250
Route 1 \LED:COM_PWM:PWMUDB:final_kill_reg\ \LED:COM_PWM:PWMUDB:final_kill_reg\/q \LED:COM_PWM:PWMUDB:status_5\/main_0 2.295
macrocell10 U(2,4) 1 \LED:COM_PWM:PWMUDB:status_5\ \LED:COM_PWM:PWMUDB:status_5\/main_0 \LED:COM_PWM:PWMUDB:status_5\/q 3.350
Route 1 \LED:COM_PWM:PWMUDB:status_5\ \LED:COM_PWM:PWMUDB:status_5\/q \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\/status_5 2.326
statusicell1 U(3,4) 1 \LED:COM_PWM:PWMUDB:sSTSReg:rstSts:stsreg\ HOLD -2.000
Clock Skew 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LED:RAM_2:ctrl_reg\/control_1 Common_1(0)_PAD 30.801
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED:RAM_2:ctrl_reg\ \LED:RAM_2:ctrl_reg\/clock \LED:RAM_2:ctrl_reg\/control_1 2.580
Route 1 \LED:Com_1\ \LED:RAM_2:ctrl_reg\/control_1 Common_1_EQN/main_0 2.311
macrocell2 U(2,4) 1 Common_1_EQN Common_1_EQN/main_0 Common_1_EQN/q 3.350
Route 1 Common_1 Common_1_EQN/q Common_1(0)/pin_input 6.360
iocell P0[1] 1 Common_1(0) Common_1(0)/pin_input Common_1(0)/pad_out 16.200
Route 1 Common_1(0)_PAD Common_1(0)/pad_out Common_1(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_2:ctrl_reg\/control_2 Common_2(0)_PAD 30.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED:RAM_2:ctrl_reg\ \LED:RAM_2:ctrl_reg\/clock \LED:RAM_2:ctrl_reg\/control_2 2.580
Route 1 \LED:Com_2\ \LED:RAM_2:ctrl_reg\/control_2 Common_2_EQN/main_0 2.315
macrocell3 U(2,4) 1 Common_2_EQN Common_2_EQN/main_0 Common_2_EQN/q 3.350
Route 1 Common_2 Common_2_EQN/q Common_2(0)/pin_input 6.331
iocell P0[2] 1 Common_2(0) Common_2(0)/pin_input Common_2(0)/pad_out 16.200
Route 1 Common_2(0)_PAD Common_2(0)/pad_out Common_2(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_2:ctrl_reg\/control_3 Common_3(0)_PAD 29.979
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED:RAM_2:ctrl_reg\ \LED:RAM_2:ctrl_reg\/clock \LED:RAM_2:ctrl_reg\/control_3 2.580
Route 1 \LED:Com_3\ \LED:RAM_2:ctrl_reg\/control_3 Common_3_EQN/main_0 2.318
macrocell4 U(2,4) 1 Common_3_EQN Common_3_EQN/main_0 Common_3_EQN/q 3.350
Route 1 Common_3 Common_3_EQN/q Common_3(0)/pin_input 5.531
iocell P0[3] 1 Common_3(0) Common_3(0)/pin_input Common_3(0)/pad_out 16.200
Route 1 Common_3(0)_PAD Common_3(0)/pad_out Common_3(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_2:ctrl_reg\/control_0 Common_0(0)_PAD 29.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(2,4) 1 \LED:RAM_2:ctrl_reg\ \LED:RAM_2:ctrl_reg\/clock \LED:RAM_2:ctrl_reg\/control_0 2.580
Route 1 \LED:Com_0\ \LED:RAM_2:ctrl_reg\/control_0 Common_0_EQN/main_0 2.308
macrocell1 U(2,4) 1 Common_0_EQN Common_0_EQN/main_0 Common_0_EQN/q 3.350
Route 1 Common_0 Common_0_EQN/q Common_0(0)/pin_input 5.496
iocell P0[0] 1 Common_0(0) Common_0(0)/pin_input Common_0(0)/pad_out 16.200
Route 1 Common_0(0)_PAD Common_0(0)/pad_out Common_0(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_0 Segment_0(0)_PAD 25.388
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_0 2.580
Route 1 Segment_0 \LED:RAM_1:ctrl_reg\/control_0 Segment_0(0)/pin_input 6.608
iocell P3[0] 1 Segment_0(0) Segment_0(0)/pin_input Segment_0(0)/pad_out 16.200
Route 1 Segment_0(0)_PAD Segment_0(0)/pad_out Segment_0(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_2 Segment_2(0)_PAD 25.016
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_2 2.580
Route 1 Segment_2 \LED:RAM_1:ctrl_reg\/control_2 Segment_2(0)/pin_input 6.236
iocell P3[2] 1 Segment_2(0) Segment_2(0)/pin_input Segment_2(0)/pad_out 16.200
Route 1 Segment_2(0)_PAD Segment_2(0)/pad_out Segment_2(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_6 Segment_6(0)_PAD 24.614
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_6 2.580
Route 1 Segment_6 \LED:RAM_1:ctrl_reg\/control_6 Segment_6(0)/pin_input 5.834
iocell P3[6] 1 Segment_6(0) Segment_6(0)/pin_input Segment_6(0)/pad_out 16.200
Route 1 Segment_6(0)_PAD Segment_6(0)/pad_out Segment_6(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_5 Segment_5(0)_PAD 24.529
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_5 2.580
Route 1 Segment_5 \LED:RAM_1:ctrl_reg\/control_5 Segment_5(0)/pin_input 5.749
iocell P3[5] 1 Segment_5(0) Segment_5(0)/pin_input Segment_5(0)/pad_out 16.200
Route 1 Segment_5(0)_PAD Segment_5(0)/pad_out Segment_5(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_4 Segment_4(0)_PAD 24.335
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_4 2.580
Route 1 Segment_4 \LED:RAM_1:ctrl_reg\/control_4 Segment_4(0)/pin_input 5.555
iocell P3[4] 1 Segment_4(0) Segment_4(0)/pin_input Segment_4(0)/pad_out 16.200
Route 1 Segment_4(0)_PAD Segment_4(0)/pad_out Segment_4(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_7 Segment_7(0)_PAD 24.332
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_7 2.580
Route 1 Segment_7 \LED:RAM_1:ctrl_reg\/control_7 Segment_7(0)/pin_input 5.552
iocell P3[7] 1 Segment_7(0) Segment_7(0)/pin_input Segment_7(0)/pad_out 16.200
Route 1 Segment_7(0)_PAD Segment_7(0)/pad_out Segment_7(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_3 Segment_3(0)_PAD 24.299
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_3 2.580
Route 1 Segment_3 \LED:RAM_1:ctrl_reg\/control_3 Segment_3(0)/pin_input 5.519
iocell P3[3] 1 Segment_3(0) Segment_3(0)/pin_input Segment_3(0)/pad_out 16.200
Route 1 Segment_3(0)_PAD Segment_3(0)/pad_out Segment_3(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:RAM_1:ctrl_reg\/control_1 Segment_1(0)_PAD 24.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \LED:RAM_1:ctrl_reg\ \LED:RAM_1:ctrl_reg\/clock \LED:RAM_1:ctrl_reg\/control_1 2.580
Route 1 Segment_1 \LED:RAM_1:ctrl_reg\/control_1 Segment_1(0)/pin_input 5.518
iocell P3[1] 1 Segment_1(0) Segment_1(0)/pin_input Segment_1(0)/pad_out 16.200
Route 1 Segment_1(0)_PAD Segment_1(0)/pad_out Segment_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ LED_PWM_Clock
Source Destination Delay (ns)
\LED:Brightness\/q Common_1(0)_PAD 29.460
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 \LED:Brightness\ \LED:Brightness\/clock_0 \LED:Brightness\/q 1.250
Route 1 \LED:Brightness\ \LED:Brightness\/q Common_1_EQN/main_1 2.300
macrocell2 U(2,4) 1 Common_1_EQN Common_1_EQN/main_1 Common_1_EQN/q 3.350
Route 1 Common_1 Common_1_EQN/q Common_1(0)/pin_input 6.360
iocell P0[1] 1 Common_1(0) Common_1(0)/pin_input Common_1(0)/pad_out 16.200
Route 1 Common_1(0)_PAD Common_1(0)/pad_out Common_1(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:Brightness\/q Common_2(0)_PAD 29.431
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 \LED:Brightness\ \LED:Brightness\/clock_0 \LED:Brightness\/q 1.250
Route 1 \LED:Brightness\ \LED:Brightness\/q Common_2_EQN/main_1 2.300
macrocell3 U(2,4) 1 Common_2_EQN Common_2_EQN/main_1 Common_2_EQN/q 3.350
Route 1 Common_2 Common_2_EQN/q Common_2(0)/pin_input 6.331
iocell P0[2] 1 Common_2(0) Common_2(0)/pin_input Common_2(0)/pad_out 16.200
Route 1 Common_2(0)_PAD Common_2(0)/pad_out Common_2(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:Brightness\/q Common_3(0)_PAD 28.631
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 \LED:Brightness\ \LED:Brightness\/clock_0 \LED:Brightness\/q 1.250
Route 1 \LED:Brightness\ \LED:Brightness\/q Common_3_EQN/main_1 2.300
macrocell4 U(2,4) 1 Common_3_EQN Common_3_EQN/main_1 Common_3_EQN/q 3.350
Route 1 Common_3 Common_3_EQN/q Common_3(0)/pin_input 5.531
iocell P0[3] 1 Common_3(0) Common_3(0)/pin_input Common_3(0)/pad_out 16.200
Route 1 Common_3(0)_PAD Common_3(0)/pad_out Common_3(0)_PAD 0.000
Clock Clock path delay 0.000
\LED:Brightness\/q Common_0(0)_PAD 28.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,4) 1 \LED:Brightness\ \LED:Brightness\/clock_0 \LED:Brightness\/q 1.250
Route 1 \LED:Brightness\ \LED:Brightness\/q Common_0_EQN/main_1 2.300
macrocell1 U(2,4) 1 Common_0_EQN Common_0_EQN/main_1 Common_0_EQN/q 3.350
Route 1 Common_0 Common_0_EQN/q Common_0(0)/pin_input 5.496
iocell P0[0] 1 Common_0(0) Common_0(0)/pin_input Common_0(0)/pad_out 16.200
Route 1 Common_0(0)_PAD Common_0(0)/pad_out Common_0(0)_PAD 0.000
Clock Clock path delay 0.000