Static Timing Analysis

Project : Basic7PE-PSOC6
Build Time : 01/06/19 12:56:49
Device : CY8C6347BZI-BLD53
Temperature : -40C
VBACKUP : 3.30
VDDA : 3.30
VDDA_CSD : 3.30
VDDD : 3.30
VDDIO_0 : 3.30
VDDIO_0_RCV : 3.30
VDDIO_1 : 3.30
VDDIO_A : 3.30
VDDQ : 3.30
VDDR_HVL_2 : 3.30
VDDR_HVL_3 : 3.30
VDD_NS : 3.30
Voltage : 3.3
vddd : 3.30
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyClk_Fast CyClk_Fast 100.000 MHz 100.000 MHz N/A
CyClk_HF0 CyClk_HF0 100.000 MHz 100.000 MHz N/A
CyClk_LF CyClk_LF 32.000 kHz 32.000 kHz N/A
CyClk_Peri CyClk_Peri 50.000 MHz 50.000 MHz N/A
CyClk_Slow CyClk_Peri 50.000 MHz 50.000 MHz N/A
SPI_SCBCLK CyClk_Peri 50.000 MHz 50.000 MHz N/A
Clock_PWM CyClk_Peri 50.000 MHz 50.000 MHz N/A
UART_BCP_SCBCLK CyClk_Peri 10.000 MHz 10.000 MHz N/A
CyFLL CyFLL 100.000 MHz 100.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 8.000 MHz 8.000 MHz N/A
CyPeriClk_App CyPeriClk_App 50.000 MHz 50.000 MHz N/A