Static Timing Analysis

Project : josh_qnet_board_wd_test
Build Time : 02/13/20 14:18:11
Device : CY8C6247BZI-D54
Temperature : -40C
VBACKUP : 3.30
VDDA : 3.30
VDDA_CSD : 3.30
VDDD : 3.30
VDDIO_0 : 3.30
VDDIO_0_RCV : 3.30
VDDIO_1 : 3.30
VDDIO_A : 3.30
VDDIO_R : 3.30
VDDQ : 3.30
VDDUSB : 3.30
VDD_NS : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyClk_Fast CyClk_Fast 100.000 MHz 100.000 MHz N/A
CyClk_HF0 CyClk_HF0 100.000 MHz 100.000 MHz N/A
CyClk_LF CyClk_LF 32.000 kHz 32.000 kHz N/A
CyClk_Peri CyClk_Peri 100.000 MHz 100.000 MHz N/A
CyClk_Slow CyClk_Peri 100.000 MHz 100.000 MHz N/A
UART_HOST_SCBCLK CyClk_Peri 1.389 MHz 1.389 MHz N/A
CyFLL CyFLL 100.000 MHz 100.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 8.000 MHz 8.000 MHz N/A
CyPeriClk_App CyPeriClk_App 100.000 MHz 100.000 MHz N/A