Static Timing Analysis

Project : Design01
Build Time : 06/04/18 09:26:17
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyMASTER_CLK 2.000 MHz 2.000 MHz 71.185 MHz
UART_1_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 48.998 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
SPI_Clk(0)_PAD SPI_Clk(0)_PAD UNKNOWN UNKNOWN 36.822 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:sync_2\/out \SPIS_1:BSPIS:TxStsReg\/status_0 71.185 MHz 14.048 485.952
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_2\ \SPIS_1:BSPIS:sync_2\/clock \SPIS_1:BSPIS:sync_2\/out 1.020
Route 1 \SPIS_1:BSPIS:miso_tx_empty_reg_fin\ \SPIS_1:BSPIS:sync_2\/out \SPIS_1:BSPIS:tx_status_0\/main_2 6.871
macrocell5 U(1,5) 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/main_2 \SPIS_1:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/q \SPIS_1:BSPIS:TxStsReg\/status_0 2.307
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:TxStsReg\/status_6 85.558 MHz 11.688 488.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_1\ \SPIS_1:BSPIS:sync_1\/clock \SPIS_1:BSPIS:sync_1\/out 1.020
Route 1 \SPIS_1:BSPIS:dpcounter_one_fin\ \SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:byte_complete\/main_0 2.625
macrocell2 U(1,5) 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/main_0 \SPIS_1:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/q \SPIS_1:BSPIS:TxStsReg\/status_6 4.193
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:TxStsReg\/status_6 86.274 MHz 11.591 488.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,5) 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_1:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:byte_complete\/main_1 2.298
macrocell2 U(1,5) 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/main_1 \SPIS_1:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/q \SPIS_1:BSPIS:TxStsReg\/status_6 4.193
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:TxStsReg\/status_0 102.020 MHz 9.802 490.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_1\ \SPIS_1:BSPIS:sync_1\/clock \SPIS_1:BSPIS:sync_1\/out 1.020
Route 1 \SPIS_1:BSPIS:dpcounter_one_fin\ \SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:tx_status_0\/main_0 2.625
macrocell5 U(1,5) 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/main_0 \SPIS_1:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/q \SPIS_1:BSPIS:TxStsReg\/status_0 2.307
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:mosi_buf_overrun_fin\/q \SPIS_1:BSPIS:RxStsReg\/status_5 102.944 MHz 9.714 490.286
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,3) 1 \SPIS_1:BSPIS:mosi_buf_overrun_fin\ \SPIS_1:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS_1:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS_1:BSPIS:mosi_buf_overrun_fin\ \SPIS_1:BSPIS:mosi_buf_overrun_fin\/q \SPIS_1:BSPIS:rx_buf_overrun\/main_1 2.292
macrocell3 U(1,3) 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/main_1 \SPIS_1:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/q \SPIS_1:BSPIS:RxStsReg\/status_5 2.322
statusicell2 U(0,3) 1 \SPIS_1:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:TxStsReg\/status_0 103.040 MHz 9.705 490.295
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,5) 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_1:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:tx_status_0\/main_1 2.298
macrocell5 U(1,5) 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/main_1 \SPIS_1:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/q \SPIS_1:BSPIS:TxStsReg\/status_0 2.307
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:RxStsReg\/status_5 104.932 MHz 9.530 490.470
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \SPIS_1:BSPIS:sync_3\ \SPIS_1:BSPIS:sync_3\/clock \SPIS_1:BSPIS:sync_3\/out 1.020
Route 1 \SPIS_1:BSPIS:mosi_buf_overrun_reg\ \SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:rx_buf_overrun\/main_0 2.338
macrocell3 U(1,3) 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/main_0 \SPIS_1:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/q \SPIS_1:BSPIS:RxStsReg\/status_5 2.322
statusicell2 U(0,3) 1 \SPIS_1:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:dpcounter_one_reg\/main_0 139.489 MHz 7.169 492.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_1\ \SPIS_1:BSPIS:sync_1\/clock \SPIS_1:BSPIS:sync_1\/out 1.020
Route 1 \SPIS_1:BSPIS:dpcounter_one_fin\ \SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:dpcounter_one_reg\/main_0 2.639
macrocell14 U(1,5) 1 \SPIS_1:BSPIS:dpcounter_one_reg\ SETUP 3.510
Clock Skew 0.000
\SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:mosi_buf_overrun_fin\/main_0 145.603 MHz 6.868 493.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \SPIS_1:BSPIS:sync_3\ \SPIS_1:BSPIS:sync_3\/clock \SPIS_1:BSPIS:sync_3\/out 1.020
Route 1 \SPIS_1:BSPIS:mosi_buf_overrun_reg\ \SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:mosi_buf_overrun_fin\/main_0 2.338
macrocell15 U(1,3) 1 \SPIS_1:BSPIS:mosi_buf_overrun_fin\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 73.643 MHz 13.579
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,5) 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/clock_0 \SPIS_1:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:mosi_to_dp\/main_4 2.296
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_4 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 1.940
Clock Skew 0.925
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 95.120 MHz 10.513
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 95.138 MHz 10.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 95.147 MHz 10.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 95.166 MHz 10.508
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 95.166 MHz 10.508
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 95.193 MHz 10.505
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 95.193 MHz 10.505
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 95.220 MHz 10.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ SETUP -0.000
Clock Skew -0.004
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 67.972 MHz 14.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:mosi_to_dp\/main_3 3.664
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_3 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 1.940
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 67.981 MHz 14.710
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:mosi_to_dp\/main_2 3.662
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_2 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 1.940
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 67.995 MHz 14.707
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:mosi_to_dp\/main_1 3.659
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_1 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 1.940
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 68.009 MHz 14.704
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:mosi_to_dp\/main_0 3.656
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_0 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 1.940
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 93.958 MHz 10.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 0.130
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 93.976 MHz 10.641
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 0.130
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 93.985 MHz 10.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ SETUP 0.130
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 94.003 MHz 10.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ SETUP 0.130
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 94.003 MHz 10.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 0.130
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 94.029 MHz 10.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 0.130
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 48.998 MHz 20.409 13021.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 5.965
macrocell10 U(0,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.654
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 49.731 MHz 20.108 13021.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 5.664
macrocell10 U(0,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.654
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 51.811 MHz 19.301 13022.366
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 5.917
macrocell10 U(0,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.654
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.270 MHz 18.093 13023.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,4) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.649
macrocell10 U(0,5) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 3.654
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 68.776 MHz 14.540 13027.127
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 6.528
macrocell11 U(1,5) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.912
statusicell3 U(1,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 69.798 MHz 14.327 13027.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 3.985
macrocell11 U(1,5) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.912
statusicell3 U(1,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxSts\/status_0 70.225 MHz 14.240 13027.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_status_0\/main_4 6.228
macrocell11 U(1,5) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.912
statusicell3 U(1,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 72.474 MHz 13.798 13027.869
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_2 6.538
datapathcell3 U(1,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxSts\/status_0 77.549 MHz 12.895 13028.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_status_0\/main_2 5.943
macrocell11 U(1,5) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.912
statusicell3 U(1,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_3 82.871 MHz 12.067 13029.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_3 7.307
macrocell18 U(1,4) 1 \UART_1:BUART:tx_state_1\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:mosi_buf_overrun_fin\/main_0 2.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \SPIS_1:BSPIS:sync_3\ \SPIS_1:BSPIS:sync_3\/clock \SPIS_1:BSPIS:sync_3\/out 0.350
Route 1 \SPIS_1:BSPIS:mosi_buf_overrun_reg\ \SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:mosi_buf_overrun_fin\/main_0 2.338
macrocell15 U(1,3) 1 \SPIS_1:BSPIS:mosi_buf_overrun_fin\ HOLD 0.000
Clock Skew 0.000
\SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:dpcounter_one_reg\/main_0 2.989
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_1\ \SPIS_1:BSPIS:sync_1\/clock \SPIS_1:BSPIS:sync_1\/out 0.350
Route 1 \SPIS_1:BSPIS:dpcounter_one_fin\ \SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:dpcounter_one_reg\/main_0 2.639
macrocell14 U(1,5) 1 \SPIS_1:BSPIS:dpcounter_one_reg\ HOLD 0.000
Clock Skew 0.000
\SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:RxStsReg\/status_5 6.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(1,3) 1 \SPIS_1:BSPIS:sync_3\ \SPIS_1:BSPIS:sync_3\/clock \SPIS_1:BSPIS:sync_3\/out 0.350
Route 1 \SPIS_1:BSPIS:mosi_buf_overrun_reg\ \SPIS_1:BSPIS:sync_3\/out \SPIS_1:BSPIS:rx_buf_overrun\/main_0 2.338
macrocell3 U(1,3) 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/main_0 \SPIS_1:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/q \SPIS_1:BSPIS:RxStsReg\/status_5 2.322
statusicell2 U(0,3) 1 \SPIS_1:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:TxStsReg\/status_0 6.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_1\ \SPIS_1:BSPIS:sync_1\/clock \SPIS_1:BSPIS:sync_1\/out 0.350
Route 1 \SPIS_1:BSPIS:dpcounter_one_fin\ \SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:tx_status_0\/main_0 2.625
macrocell5 U(1,5) 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/main_0 \SPIS_1:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/q \SPIS_1:BSPIS:TxStsReg\/status_0 2.307
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:TxStsReg\/status_0 7.205
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,5) 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_1:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:tx_status_0\/main_1 2.298
macrocell5 U(1,5) 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/main_1 \SPIS_1:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/q \SPIS_1:BSPIS:TxStsReg\/status_0 2.307
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_1:BSPIS:mosi_buf_overrun_fin\/q \SPIS_1:BSPIS:RxStsReg\/status_5 7.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,3) 1 \SPIS_1:BSPIS:mosi_buf_overrun_fin\ \SPIS_1:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS_1:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS_1:BSPIS:mosi_buf_overrun_fin\ \SPIS_1:BSPIS:mosi_buf_overrun_fin\/q \SPIS_1:BSPIS:rx_buf_overrun\/main_1 2.292
macrocell3 U(1,3) 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/main_1 \SPIS_1:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS_1:BSPIS:rx_buf_overrun\ \SPIS_1:BSPIS:rx_buf_overrun\/q \SPIS_1:BSPIS:RxStsReg\/status_5 2.322
statusicell2 U(0,3) 1 \SPIS_1:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:TxStsReg\/status_6 8.518
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_1\ \SPIS_1:BSPIS:sync_1\/clock \SPIS_1:BSPIS:sync_1\/out 0.350
Route 1 \SPIS_1:BSPIS:dpcounter_one_fin\ \SPIS_1:BSPIS:sync_1\/out \SPIS_1:BSPIS:byte_complete\/main_0 2.625
macrocell2 U(1,5) 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/main_0 \SPIS_1:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/q \SPIS_1:BSPIS:TxStsReg\/status_6 4.193
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:TxStsReg\/status_6 9.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,5) 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/clock_0 \SPIS_1:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS_1:BSPIS:dpcounter_one_reg\ \SPIS_1:BSPIS:dpcounter_one_reg\/q \SPIS_1:BSPIS:byte_complete\/main_1 2.298
macrocell2 U(1,5) 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/main_1 \SPIS_1:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS_1:BSPIS:byte_complete\ \SPIS_1:BSPIS:byte_complete\/q \SPIS_1:BSPIS:TxStsReg\/status_6 4.193
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS_1:BSPIS:sync_2\/out \SPIS_1:BSPIS:TxStsReg\/status_0 10.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 \SPIS_1:BSPIS:sync_2\ \SPIS_1:BSPIS:sync_2\/clock \SPIS_1:BSPIS:sync_2\/out 0.350
Route 1 \SPIS_1:BSPIS:miso_tx_empty_reg_fin\ \SPIS_1:BSPIS:sync_2\/out \SPIS_1:BSPIS:tx_status_0\/main_2 6.871
macrocell5 U(1,5) 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/main_2 \SPIS_1:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_status_0\ \SPIS_1:BSPIS:tx_status_0\/q \SPIS_1:BSPIS:TxStsReg\/status_0 2.307
statusicell1 U(1,5) 1 \SPIS_1:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 5010.069
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,5) 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/clock_0 \SPIS_1:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:mosi_to_dp\/main_4 2.296
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_4 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -1.570
Clock Skew 0.925
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 5005.792
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 5005.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 5005.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 5005.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 5005.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 5005.800
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/f1_load 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -3.390
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 5005.801
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 5005.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/f1_load 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -3.390
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:sR16:Dp:u1\/sor \SPIS_1:BSPIS:sR16:Dp:u0\/sil 3.676
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ \SPIS_1:BSPIS:sR16:Dp:u1\/clock \SPIS_1:BSPIS:sR16:Dp:u1\/sor 4.900
Route 1 \SPIS_1:BSPIS:sR16:Dp:u1.sor__sig\ \SPIS_1:BSPIS:sR16:Dp:u1\/sor \SPIS_1:BSPIS:sR16:Dp:u0\/sil 0.000
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -1.220
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 6.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -2.260
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 6.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 2.608
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -2.260
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 6.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -2.260
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 6.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -2.260
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 6.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 2.611
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -2.260
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 6.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u0\/cs_addr_0 2.608
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ HOLD -2.260
Clock Skew -0.004
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 6.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 2.614
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -2.260
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 6.933
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 2.616
macrocell1 U(0,4) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR16:Dp:u1\/cs_addr_0 2.607
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -2.260
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 9.874
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,4) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:mosi_to_dp\/main_0 3.656
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_0 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ HOLD -1.570
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.634
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.444
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 3.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,3) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 1.510
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.288
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_1\/main_1 3.837
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,4) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_1\/main_1 2.587
macrocell18 U(1,4) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_0\/main_1 3.839
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,4) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
macrocell19 U(1,4) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_state_0\/main_1 2.589
macrocell19 U(1,4) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.841
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.591
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_6 3.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:txn\/main_6 2.614
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_2\/main_5 3.866
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:tx_state_2\/main_5 2.616
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 4.036
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 3.846
macrocell18 U(1,4) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 4.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 4.024
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 4.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(0,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:txn\/main_4 2.976
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPI_Clk(0)_PAD
Source Destination Delay (ns)
MOSI(0)_PAD \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 10.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MOSI(0)_PAD MOSI(0)_PAD MOSI(0)/pad_in 0.000
iocell3 P3[0] 1 MOSI(0) MOSI(0)/pad_in MOSI(0)/fb 6.324
Route 1 Net_1 MOSI(0)/fb \SPIS_1:BSPIS:mosi_to_dp\/main_5 10.297
macrocell8 U(0,5) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_5 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR16:Dp:u1\/route_si 3.818
datapathcell2 U(0,4) 1 \SPIS_1:BSPIS:sR16:Dp:u1\ SETUP 1.940
Clock Clock path delay -15.428
MOSI(0)_PAD \SPIS_1:BSPIS:mosi_tmp\/main_0 4.330
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 MOSI(0)_PAD MOSI(0)_PAD MOSI(0)/pad_in 0.000
iocell3 P3[0] 1 MOSI(0) MOSI(0)/pad_in MOSI(0)/fb 6.324
Route 1 Net_1 MOSI(0)/fb \SPIS_1:BSPIS:mosi_tmp\/main_0 10.849
macrocell16 U(0,5) 1 \SPIS_1:BSPIS:mosi_tmp\ SETUP 3.510
Clock Clock path delay -16.353
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\LED1:Sync:ctrl_reg\/control_0 Pin_1(0)_PAD 23.739
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \LED1:Sync:ctrl_reg\ \LED1:Sync:ctrl_reg\/busclk \LED1:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_58 \LED1:Sync:ctrl_reg\/control_0 Pin_1(0)/pin_input 5.798
iocell2 P2[1] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.891
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ SPI_Clk(0)_PAD
Source Destination Delay (ns)
\SPIS_1:BSPIS:sR16:Dp:u0\/so_comb MISO(0)_PAD 46.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,4) 1 \SPIS_1:BSPIS:sR16:Dp:u0\ \SPIS_1:BSPIS:sR16:Dp:u0\/clock \SPIS_1:BSPIS:sR16:Dp:u0\/so_comb 6.410
Route 1 Net_45 \SPIS_1:BSPIS:sR16:Dp:u0\/so_comb MISO(0)/pin_input 9.601
iocell1 P3[3] 1 MISO(0) MISO(0)/pin_input MISO(0)/pad_out 14.591
Route 1 MISO(0)_PAD MISO(0)/pad_out MISO(0)_PAD 0.000
Clock Clock path delay 15.432
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q UART_TX(0)_PAD 30.715
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_59/main_0 2.592
macrocell9 U(0,3) 1 Net_59 Net_59/main_0 Net_59/q 3.350
Route 1 Net_59 Net_59/q UART_TX(0)/pin_input 6.556
iocell5 P12[7] 1 UART_TX(0) UART_TX(0)/pin_input UART_TX(0)/pad_out 16.967
Route 1 UART_TX(0)_PAD UART_TX(0)/pad_out UART_TX(0)_PAD 0.000
Clock Clock path delay 0.000