Static Timing Analysis

Project : 7Eyes_Dice_CapSence_Buzz
Build Time : 07/15/20 15:19:03
Device : CY8C6347BZI-BLD53
Temperature : -40C
VBACKUP : 3.30
VDDA : 3.30
VDDA_CSD : 3.30
VDDD : 3.30
VDDIO_0 : 3.30
VDDIO_0_RCV : 3.30
VDDIO_1 : 3.30
VDDIO_A : 3.30
VDDQ : 3.30
VDDR_HVL_2 : 3.30
VDDR_HVL_3 : 3.30
VDD_NS : 3.30
Voltage : 3.3
vddd : 3.30
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyClk_Fast CyClk_Fast 100.000 MHz 100.000 MHz N/A
CyClk_HF0 CyClk_HF0 100.000 MHz 100.000 MHz N/A
CyClk_LF CyClk_LF 32.000 kHz 32.000 kHz N/A
CyClk_Peri CyClk_Peri 50.000 MHz 50.000 MHz N/A
CyClk_Slow CyClk_Peri 50.000 MHz 50.000 MHz N/A
CapSense_ModClk CyClk_Peri 196.078 kHz 196.078 kHz N/A
Clock CyClk_Peri 10.000 kHz 10.000 kHz N/A
Clock_1 CyClk_Peri 1.000 MHz 1.000 MHz N/A
CyFLL CyFLL 100.000 MHz 100.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 8.000 MHz 8.000 MHz N/A
CyPeriClk_App CyPeriClk_App 50.000 MHz 50.000 MHz N/A
\PWM_1:TCPWM\/line \PWM_1:TCPWM\/line UNKNOWN UNKNOWN 331.895 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_83/q Net_83/main_2 331.895 MHz 3.013
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
macrocell8 U(0,1) 1 Net_83 Net_83/q Net_83/main_2 1.283
macrocell8 U(0,1) 1 Net_83 SETUP 1.090
Clock Skew 0.000
Net_83/q Net_561/main_2 331.895 MHz 3.013
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_561/main_2 1.283
macrocell9 U(0,1) 1 Net_561 SETUP 1.090
Clock Skew 0.000
Net_112/q Net_83/main_0 358.938 MHz 2.786
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 Net_112 Net_112/clock_0 Net_112/q 0.530
Route 1 Net_112 Net_112/q Net_83/main_0 1.196
macrocell8 U(0,1) 1 Net_83 SETUP 1.060
Clock Skew 0.000
Net_112/q Net_561/main_0 358.938 MHz 2.786
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 Net_112 Net_112/clock_0 Net_112/q 0.530
Route 1 Net_112 Net_112/q Net_561/main_0 1.196
macrocell9 U(0,1) 1 Net_561 SETUP 1.060
Clock Skew 0.000
Net_561/q Net_83/main_1 381.534 MHz 2.621
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 Net_561 Net_561/clock_0 Net_561/q 0.420
Route 1 Net_561 Net_561/q Net_83/main_1 1.271
macrocell8 U(0,1) 1 Net_83 SETUP 0.930
Clock Skew 0.000
Net_561/q Net_561/main_1 381.534 MHz 2.621
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 Net_561 Net_561/clock_0 Net_561/q 0.420
macrocell9 U(0,1) 1 Net_561 Net_561/q Net_561/main_1 1.271
macrocell9 U(0,1) 1 Net_561 SETUP 0.930
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_112/q Net_83/main_0 1.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 Net_112 Net_112/clock_0 Net_112/q 0.400
Route 1 Net_112 Net_112/q Net_83/main_0 1.196
macrocell8 U(0,1) 1 Net_83 HOLD 0.000
Clock Skew 0.000
Net_112/q Net_561/main_0 1.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 Net_112 Net_112/clock_0 Net_112/q 0.400
Route 1 Net_112 Net_112/q Net_561/main_0 1.196
macrocell9 U(0,1) 1 Net_561 HOLD 0.000
Clock Skew 0.000
Net_561/q Net_83/main_1 1.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 Net_561 Net_561/clock_0 Net_561/q 0.340
Route 1 Net_561 Net_561/q Net_83/main_1 1.271
macrocell8 U(0,1) 1 Net_83 HOLD 0.000
Clock Skew 0.000
Net_561/q Net_561/main_1 1.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 Net_561 Net_561/clock_0 Net_561/q 0.340
macrocell9 U(0,1) 1 Net_561 Net_561/q Net_561/main_1 1.271
macrocell9 U(0,1) 1 Net_561 HOLD 0.000
Clock Skew 0.000
Net_83/q Net_83/main_2 1.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.520
macrocell8 U(0,1) 1 Net_83 Net_83/q Net_83/main_2 1.283
macrocell8 U(0,1) 1 Net_83 HOLD 0.000
Clock Skew 0.000
Net_83/q Net_561/main_2 1.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.520
Route 1 Net_83 Net_83/q Net_561/main_2 1.283
macrocell9 U(0,1) 1 Net_561 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ \PWM_1:TCPWM\/line
Source Destination Delay (ns)
Net_112/q RED(0)_PAD 29.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 Net_112 Net_112/clock_0 Net_112/q 0.530
Route 1 Net_112 Net_112/q Net_173/main_0 3.684
macrocell4 U(0,4) 1 Net_173 Net_173/main_0 Net_173/q 0.800
Route 1 Net_173 Net_173/q RED(0)/pin_input 14.037
iocell11 P13[7] 1 RED(0) RED(0)/pin_input RED(0)/pad_out 2.757
Route 1 RED(0)_PAD RED(0)/pad_out RED(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q LED4(0)_PAD 27.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_175/main_2 1.283
macrocell3 U(0,1) 1 Net_175 Net_175/main_2 Net_175/q 0.970
Route 1 Net_175 Net_175/q LED4(0)/pin_input 14.549
iocell7 P9[7] 1 LED4(0) LED4(0)/pin_input LED4(0)/pad_out 2.757
Route 1 LED4(0)_PAD LED4(0)/pad_out LED4(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q LED6(0)_PAD 26.458
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_581/main_2 1.158
macrocell2 U(0,1) 1 Net_581 Net_581/main_2 Net_581/q 1.260
Route 1 Net_581 Net_581/q LED6(0)/pin_input 12.970
iocell9 P9[4] 1 LED6(0) LED6(0)/pin_input LED6(0)/pad_out 2.757
Route 1 LED6(0)_PAD LED6(0)/pad_out LED6(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q LED2(0)_PAD 25.807
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_521/main_2 1.158
macrocell1 U(0,1) 1 Net_521 Net_521/main_2 Net_521/q 1.230
Route 1 Net_521 Net_521/q LED2(0)/pin_input 12.349
iocell5 P9[6] 1 LED2(0) LED2(0)/pin_input LED2(0)/pad_out 2.757
Route 1 LED2(0)_PAD LED2(0)/pad_out LED2(0)_PAD 0.000
Clock Clock path delay 7.673
Net_561/q BLE(0)_PAD 24.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 Net_561 Net_561/clock_0 Net_561/q 0.420
Route 1 Net_561 Net_561/q Net_557/main_0 1.130
macrocell5 U(0,1) 1 Net_557 Net_557/main_0 Net_557/q 1.160
Route 1 Net_557 Net_557/q BLE(0)/pin_input 11.495
iocell13 P11[1] 1 BLE(0) BLE(0)/pin_input BLE(0)/pad_out 2.757
Route 1 BLE(0)_PAD BLE(0)/pad_out BLE(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q ORG(0)_PAD 24.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_159/main_0 1.158
macrocell6 U(0,1) 1 Net_159 Net_159/main_0 Net_159/q 1.110
Route 1 Net_159 Net_159/q ORG(0)/pin_input 10.629
iocell12 P1[5] 1 ORG(0) ORG(0)/pin_input ORG(0)/pad_out 3.301
Route 1 ORG(0)_PAD ORG(0)/pad_out ORG(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q LED1(0)_PAD 23.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_521/main_2 1.158
macrocell1 U(0,1) 1 Net_521 Net_521/main_2 Net_521/q 1.230
Route 1 Net_521 Net_521/q LED1(0)/pin_input 10.500
iocell4 P9[1] 1 LED1(0) LED1(0)/pin_input LED1(0)/pad_out 2.757
Route 1 LED1(0)_PAD LED1(0)/pad_out LED1(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q LED5(0)_PAD 23.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_581/main_2 1.158
macrocell2 U(0,1) 1 Net_581 Net_581/main_2 Net_581/q 1.260
Route 1 Net_581 Net_581/q LED5(0)/pin_input 10.181
iocell8 P9[2] 1 LED5(0) LED5(0)/pin_input LED5(0)/pad_out 2.757
Route 1 LED5(0)_PAD LED5(0)/pad_out LED5(0)_PAD 0.000
Clock Clock path delay 7.673
Net_83/q LED3(0)_PAD 22.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_83 Net_83/clock_0 Net_83/q 0.640
Route 1 Net_83 Net_83/q Net_175/main_2 1.283
macrocell3 U(0,1) 1 Net_175 Net_175/main_2 Net_175/q 0.970
Route 1 Net_175 Net_175/q LED3(0)/pin_input 9.119
iocell6 P9[0] 1 LED3(0) LED3(0)/pin_input LED3(0)/pad_out 2.757
Route 1 LED3(0)_PAD LED3(0)/pad_out LED3(0)_PAD 0.000
Clock Clock path delay 7.673
Net_112/q LED0(0)_PAD 22.187
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 Net_112 Net_112/clock_0 Net_112/q 0.530
Route 1 Net_112 Net_112/q LED0(0)/pin_input 11.227
iocell3 P9[5] 1 LED0(0) LED0(0)/pin_input LED0(0)/pad_out 2.757
Route 1 LED0(0)_PAD LED0(0)/pad_out LED0(0)_PAD 0.000
Clock Clock path delay 7.673