Answer:
Question: When does the Arm bit (bit 0) of the Host Control Register (00H, 08H) clear? The description says it clears when the "transfer is complete", what does that mean exactly?
Response: The Arm bit clears at the same time and under the same conditions as the USBA and USBB Done interrupts (Bits 0 and 1 in Interrupt Status Register 0DH). The conditions of both clearing the Arm bit and triggering either USBA or USBB done are defined as any event in the USB Status Register (03H and 0BH) occuring.
