The PKTEND pin can be asserted ANYTIME. There is no specific timing requirement that needs to be met for asserting PKTEND signal with regards to asserting the SLWR signal. PKTEND can be asserted with the last data value or thereafter. The only consideration is the setup time tSPE and the hold time tPEH must be met.]
In synchronous mode also, the external master may assert the PKTEND pin anytime. PKTEND can be asserted with the last data byte writen to the FIFO or thereafter. The only consideration is the setup time and the hold time must be met. The number of data bytes committed includes the last byte written to the FIFO. Both the data value and the PKTEND signal can be clocked on the same rising edge of IFCLK. Or PKTEND can be asserted in subsequent clock cycles. The number of packets committed include (only if SLWR is also in an asserted state during the same rising edge of the IFCLK) the byte written last to the FIFO on the same rising edge of IFCLK that PKTEND is asserted. The FIFOADDR lines should be held constant during the PKTEND assertion.
In asynchronous mode, if PKTEND pin is asserted with the pulse width requirements as specified in the datasheet, whatever is in the FIFO will be committed to the host. The external device should be designed to not assert SLWR and the PKTEND signal at the same time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum de-asserted pulse width. The FIFOADDR lines are to be held constant during the PKTEND assertion.