Latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver.

Question: What is the latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver?

 

Answer:

While this response focusses on the CY7C924ADX, the same numbers apply to the CY7C9689 latency.

When the internal FIFOs are disabled (FIFOBYP is LOW), the input data is stored in the transmitter input register on the rising edge of REFCLK, making this time-zero. When configured for 8-bit mode, approximately 31 bit-times (i.e., 31 times the period of REFCLK÷10) following this, the first encoded bit of that character will emerge from the OUTA± and OUTB± pins.

After the transit time of the serial link (which can be significant), that bit will appear at the receiver. Transit times for typical serial links include the propagation delay of the optical modules (typically 5-10 ns for the pair), if any, and the propagation rate in the link media (i.e., approximately 1 ns/ft in copper, and 2 ns/ft in multi-mode optical cable).

Due to clocking variations in the high-speed PLL circuitry and framer logic, a best case minimum latency bound and worst case maximum latency bound is possible within the Receiver. For the best case scenario, approximately 35 bit-times after the first data bit is presented at the input of the receiver plus a minimum delay of 2 ns through the parallel output drivers, data appears at the RXDATA or RXCMD outputs relative to RXCLK. For the worst case scenario, approximately 46 bit-times after the first data bit is received at the input of the receiver plus a maximum delay of 15 ns through the output driver circuitry, data appears at the RXDATA or RXCMD outputs relative to RXCLK.

In 8-bit mode, the total latency of a CY7C924ADX Tx/Rx pair is approximately the link delay plus 66 bit-times and 2 ns best case, or the link delay plus 77 bit-times and 15 ns worst case. In 10-bit mode the latency through the transmitter is proximately 34 bit-times (i.e., 34 times the period of REFCLK÷12).

In the Receiver a similar best case minimum latency bound and worst case maximum latency bound is possible. For the best case scenario, approximately 41 bit-times after the first data bit is received at the input of the receiver plus a minimum delay of 2 ns through the output driver circuitry, data appears at the RXDATA or RXCMD outputs relative to RXCLK. For the worst case scenario, approximately 54 bit-times after the first data bit is received at the input of the receiver plus a maximum delay of 15 ns through the output driver circuitry, data appears at the RXDATA or RXCMD outputs relative to RXCLK.

Correspondingly in 10-bit mode, the total latency of a CY7C924ADX Tx/Rx pair is approximately the link delay plus 75 bit-times plus 2 ns best case, or the link delay plus 88 bit-times plus 15 ns worst case.

When the FIFOs are enabled (FIFOBYP is HIGH) additional FIFO latency is encountered in the Transmit and Receive data paths. Both transmit and receive FIFOs achieve minimal latency when the TXCLK and RXCLK rates are slower than the REFCLK rate; otherwise, the time it takes to transmit a new character is lengthened by the additional time needed to transmit the previously stored characters. In 8-bit mode, with an initial empty transmit and receive FIFO, the transmit FIFO adds 8 bit-times, plus 2 additional TXCLK cycles to the overall delay, while the receive FIFO adds 1 bit-time, plus 4 additional RXCLK cycles to the overall delay. In 10-bit mode, with an initial empty transmit and receive FIFO, the transmit FIFO adds 9 bit-times, plus 2 additional TXCLK cycles to the overall delay, while the receive FIFO adds 1 bit-time, plus 4 additional RXCLK cycles to the overall delay.

Useful Links:
 TAXI- compatible HOTLink Transceiver Datasheet (CY7C9689A)

 200 Mbps HOTLink Transceiver Datasheet (CY7C924ADX)