- How many wait states are generated for typical accesses?
- What factors contribute to wait states?
The PCI-DP contains two basic sets of resources: the Dual-Port memory and the Operations Registers (including the FIFO). Accesses from the PCI bus or the Local bus, may incur wait states generated by the PCI-DP when accessing these resources. The external source may also insert wait states in an access. The PCI bus may deassert IRDY# to insert wait states and the Local bus may deassert either of the Ready In signals (RDY_IN and RDY_IN#) to insert wait states. For this note, PCI-DP generated wait states are discussed with particular focus on Local bus wait states. The PCI-DP indicates a Local bus wait state by deasserting the RDY_OUT# output.
The PCI-DP exhibits a fixed number of wait states for access to it's Dual-Port memory. For all other accesses, a variable number of wait states are possible. The Local bus is a synchronous interface and uses the CLKIN input as its clock. All Local bus access to any resources within the PCI-DP are in the Local bus clock domain. When Local bus Direct Access to the PCI bus is used, the PCI access is, of course, in the PCI clock domain. The PCI bus is a synchronous interface and uses the CLK input as its clock. Its access to the Dual-Port memory is in the PCI bus clock domain. It's access to the other PCI-DP resources is converted to the Local bus clock domain for internal access and arbitration and then returned to the PCI clock domain to conclude the transaction.
There is no access arbitration for the Dual-Ported memory of the PCI-DP; it may be concurrently accessed via the PCI bus and Local bus interfaces. It is up to the user to consider the effects of contention when both PCI bus and Local bus interfaces access the same DWORD memory location, (or any concurrent byte access within the same DWORD), where at least one access is a write to the memory. Once the first data is returned, there are zero wait states for subsequent dataphases in the same (burst) bus transaction, unless the external interface throttles access by inserting its own wait state. For target read accesses, there is an exception to the zero wait states of subsequent data phases. If the burst passes a 64-byte (16 DWORD) boundary, the Local bus will incur a single wait state and the PCI bus will incur a Target Disconnect. The datasheet explains the 64-byte boundary in a section entitled "Dual Port Shared Memory" located in the chapter entitled "CY7C09449PV Operations".
There is arbitration of all other accesses to the PCI-DP resources. Generally, all Operations Register and FIFO resources are available to either interface, PCI bus or Local bus. The actual arbitration takes place in the Local bus clock domain. Arbitration is on the entire block of resources. That is, if any interface is accessing any register or FIFO, then the other interface will not have access to any register or FIFO. Even if the two registers are different or one is a register and the other is a FIFO, the interface will be held off from its access until the first interface has completed access.
For the PCI bus and for other than Dual-Port memory accesses, only one DWORD is accessed during any transaction. That is, a Target Disconnect is issued during any burst attempt to Operations Register or FIFO resources. If the resource is held by the Local bus, then the PCI-DP will return a Target Retry until the resource becomes available to the PCI bus interface. For the Local bus, there is no target retry function as with PCI. If the PCI bus holds the resource, the Local bus will incur wait states until the resource becomes available.
Note that the Arbitration Utility Flag Register (ARB_FLAGS) has no direct impact upon this arbitration within the PCI-DP. These flags exist as a software and systems tool to control arbitration to resources inside or outside the PCI-DP. They can be a useful tools to manage resource access. For instance, they could be used to control which software processes have access to various blocks of the PCI-DP dual-port memory. But in terms of PCI-DP resource access, these flags have no impact to any of the PCI-DP's arbitration logic for resources other than the ARB_FLAGS, themselves.
Finally, for an example to illustrate the Local bus wait states, see the datasheet's Timing Diagram for the "Basic 8-bit Interface". In general and in a condition without resource contention, there are two wait states for any read or write access to any of the PCI-DP resources. Specifically, the following describe the wait states for the Dual-Port memory and the wait states for the other resources of the PCI-DP:
The number of wait states for a Dual-Port memory access is two CLKIN cycles from detection of the start of the basic transaction, (both SELECT# and STROBE asserted). All subsequent dataphases will burst continuous with zero wait states unless either of the Ready In signals is deasserted or, and only for the case of reads, the 64-byte boundary is crossed (which inserts one wait state to the read access).
The number of wait states for any other access (not to the Dual-Port memory) is two CLKIN cycles from detection of the start of the basic transaction, (both SELECT# and STROBE asserted), if there is no resource contention with the PCI bus interface. If the PCI bus is accessing any of these resources regardless of specific register or FIFO, then additional wait states will occur until the PCI transaction complete