No. It is not possible to use the single clock to latch in the return data from the FPGA. If you look at the echo clock to data valid time, there is 200ps guaranteed time from the data valid to the echo clock and the hold time is negative. So, after the data is invalid, the echo clock will go low. This holds true for the rising edge of the next echo clock (CQ# as well). So, there is actually some time gap from the falling edge of one echo(CQ) clock to the rising edge of the next one(CQ#). Hence, you cannot use one single clock to capture of both edges.