Edge Align feature of MoBL CLock, CY2545 and CY2547 clock generators

Question: What is the Edge Align feature of the MoBL Clock, CY2545 and CY2547 clock generators?

 

Answer:

Edge aligning clock outputs means synchronizing selected output clocks on the rising edge.  The outputs may be the same frequency or they may be different frequencies.  If they are different frequencies, they must be "related frequencies".  For example, a 20 MHz clock, a 40 MHz clock and a 60 MHz clock can all be derived from one PLL running at 240 MHz.  Further limitations are described below.

Alignment indicates basic phase alignment. Output-to-output skew is not zero, and may be as much as 700 ps between certain outputs.

Advantage:

The Edge Align feature ensures a consistent phase relationship across multiple clock outputs.

Without Edge Align:

When the Edge Align feature is disabled, the outputs will not have a consistent or predictable phase relationship, even if they are brought out of the same PLL. This is because of the output dividers are normally not synchronized.

How to Enable:

This feature can be enabled via the I2C interface by setting the least significant bit (LSB) of particular clock output control bytes to '1', and setting the PLL_Sync_EnN bit for the particular PLL to '0'.

Note: The remaining bits of the specified output byte are related to Output Enable (OE) and drive strength of the output.  Care must be taken to keep these remaining bits unchanged while setting the edge align bit. Likewise, the PLL control byte, CCH, has bits that are used for other purposes.

Different parts of CY254xx family clock generators and MoBL clocks have different numbers of outputs and PLLs.  The specific clock output control byte addresses and PLL control bits are mentioned in the table below.  Though the edge align feature is available for all devices in these product families, this article limits itself to describing those devices with an I2C interface.

 
                                                                                                                                                                                                                                                                                                                                               
   
     CY254xx Family Parts
  
   
     Part#
  
   
     Outputs
  
   
     Output Byte Address
  
   
     PLLs
  
   
     PLL Byte [Bit] Address
  
   
     CY2545
  
   
     CLK1-CLK8
  
   
     C8H-C7H,  C5H-C0H
  
   
     PLL1-PLL4
  
   
     CCH [1, 3, 5, 7]
  
   
     CY2547
  
   
     CLK1-CLK8
  
   
     C8H-C7H,  C5H-C0H
  
   
     PLL1-PLL4
  
   
     CCH [1, 3, 5, 7]
  
   
     MoBL Clocks
  
   
     Part#
  
   
     Outputs
  
   
     Output Byte Address
  
   
     PLLs
  
   
     PLL Byte [bit] Address
  
   
     M200
  
   
     CLK1-CLK3
  
   
     C8H, C3H, C0H
  
   
     PLL1-PLL2
  
   
     CCH [5, 7]
  
   
     M500
  
   
     CLK1-CLK3
  
   
     C8H, C3H, C0H
  
   
     PLL1-PLL2
  
   
     CCH [5, 7]
  
   
     M300
  
   
     CLK1-CLK3
  
   
     C8H, C3H, C0H
  
   
     PLL1-PLL3
  
   
     CCH [1, 5, 7]
  
   
     M600
  
   
     CLK1-CLK3
  
   
     C8H, C3H, C0H
  
   
     PLL1-PLL3
  
   
     CCH [1, 5, 7]
  
   
     M3000
  
   
     CLK1-CLK8
  
   
     C8H-C7H,  C5H-C0H
  
   
     PLL1-PLL3
  
   
     CCH [1, 5, 7]
  
   
     M6000
  
   
     CLK1-CLK8
  
   
     C8H-C7H,  C5H-C0H
  
   
     PLL1-PLL3
  
   
     CCH [1, 5, 7]
  
   
     M4000
  
   
     CLK1-CLK8
  
   
     C8H-C7H,  C5H-C0H
  
   
     PLL1-PLL4
  
   
     CCH [1, 3, 5, 7]
  
   
     M8000
  
   
     CLK1-CLK8
  
   
     C8H-C7H,  C5H-C0H
  
   
     PLL1-PLL4
  
   
     CCH [1, 3, 5, 7]
  

 Note: The bits in each control byte are numbered from 0 to 7.

Limitations:

To use the edge align feature, the following rules need to be followed:

1.  Aligned outputs must be driven from the same PLL.  Conversely, because there is no synchronization between PLLs, outputs coming from multiple PLLs cannot be aligned.

2.  Each output path has two dividers in series: a pre-scalar and a linear divider.  The output frequency is equal to the PLL frequency divided by the output dividers.  The PLL frequency range is 100 MHz to 400 MHz.

2a.  Pre-scalar divider for each aligned output is set to divide-by-one.

2b.  Linear divider for each aligned output is set to divide-by-2, -4, -6, or -12.

3.  Frequency Select (FS) pin options are not available for edge aligned clock outputs.