The continuous time blocks have a latch for the comparator bus output. This latch synchronizes the output with the column clock i.e. the output of the comparator changes only during the clock edge (selected by the Cphase bit in the ACBxxCR2 register). Note that the latch may also be configured as transparent (i.e. the output changes immediately as the input is changed) by setting the CLatch bit in the ACBxxCR2 register to 0.