Choice of reference voltage for accurate ADC measurements in PSoC® 3, PSoC 4 and PSoC 5LP Devices – KBA84753

Version: *A


Question: How can I choose the reference voltage for my ADC? What are the best practices to get the best possible accuracy?



The choice of reference voltage greatly impacts the ADC performance since the noise introduced by the reference degrades the SNR of the system, thereby reducing the effective resolution (flicker-free bits).

In PSoC ® 3, PSoC 4 and PSoC 5LP, ADC’s have selectable analog voltage reference. We can select one of the three modes:

  1.   Internal reference that is buffered and unfiltered
  2.   Internal reference that is buffered and filtered
  3.   External reference

In PSoC 3 (CY8C36xx, CY8C38xx) and PSoC 5LP (CY8C56xx, CY8C58xx), the internal reference has an accuracy of ±0.1% and a maximum temperature drift of 30ppm/ºC. This accuracy is sufficient for most applications. In PSoC 3 (CY8C32xx, CY8C34xx), PSoC 4 and PSoC 5LP (CY8C52xx, CY8C54xx), the internal reference has only ±1% accuracy. So, in these devices, we need to go for an external precision voltage reference if an accuracy better than ±1% is needed before calibration.

We can connect a by-pass capacitor at both (Del-Sig and SAR) ADC’s reference input (see ADC component’s datasheet to find-out the pins where the capacitor should be connected) to suppress the noise induced by digital switching. The recommended value of this capacitor is between 0.01μF and 10μF. Use of larger capacitance, helps in reducing the noise better but also affects the settling time of the reference voltage. The Table 1 shows the recommended value of the capacitor for a given resolution.

Table 1: Selection of bypass capacitor value for a given resolution

      Resolution (bits)
      Bypass Capacitor Value (μF)
      0.1 to 1.0
      0.1 to 1.0
      1.0 to 10.0

To obtain the best possible SNR from the ADC, the input signal range should match the ADC’s input voltage range. If the input signal swing (peak-peak variation) is much less compared to the ADC’s input range, we need to amplify the input signal to match the ADC’s input range. In those cases, we would use PGA’s gain or the internal buffer’s gain (only in case of Delta-Sigma ADC) and the modulator gain (only in case of Delta-Sigma ADC).

Note: SAR ADC doesn’t have a dedicated internal buffer. Hence, we need to use a buffer (either internal to PSoC or external).

Then, how should I split the gain needed across the three (PGA, internal buffer and modulator)?

The answer is: Modulator Gain > ADC’s Internal Buffer Gain > PGA gain

The modulator gain is set based on the input voltage range that we choose for the Delta-Sigma ADC. The Table 2 shows the modulator gain for various input ranges.

Table 2: Delta-Sigma ADC’s input range selection vs Modulator Gain

     Input Range
     Modulator Gain
     Input ± 6*Vref
     Input ± 2*Vref
     Input ± Vref
     Input ± Vref/2
     Input ± Vref/4
     Input ± Vref/8
     Input ± Vref/16

The best gain accuracy for the modulator is obtained when it operates in unity gain.

Note: What is modulator gain in Delta-Sigma ADC?

Delta-Sigma modulator is a switched-capacitor block with input and feedback capacitors around Op-Amps. The sizing of these capacitors will determine the amplification of the input signal. Based on the input voltage selection, PSoC Creator will determine the sizes of these capacitors on its own and use them. As there are limited set of input and feedback capacitors available only certain gain factors are available.

The application note AN84783 shows how to increase the accuracy of measurements using the 20-bit Delta-Sigma ADC in PSoC® 3 and PSoC 5LP. Major topics include effective resolution, gain and offset errors, non-linearity, and accuracy improvement techniques. A spreadsheet is provided to assist with ADC performance analysis and optimizing ADC Component configuration. Please visit the link ( to get this application note, its associated project and the spreadsheet tool.