Using the external master to control CY7C68001 will trigger a READY interrupt to the external master to let it know that it is ready to be interfaced with and needs the descriptor information for enumerating. The external master must provide the descriptor bytes accordingly. Please note that the external master must make sure to write each of the descriptor byte within 360 ns from the time the READY is asserted after having written the last byte. Failing to do so will result in improper enumeration of the SX2. Also note that once the address 0x30 (descriptor) has been addressed, the external master must provide the "entire" descriptor information all at once meeting the 360 ns maximum delay between each write.