Question: What are IRR/ODR, their functionality and benefits?
Answer:
Benefits: Why is it good to have IRR and ODR.
The Input Read Register (IRR) and the Output Drive Register (ODR) are designed specifically for the systems with area and power constraints. Assume a setup where the MoBL dual port interfaces with one or two processors. The IRR and the ODR allow one or both the processors to monitor and/or drive a number of external binary input devices without sacrificing any additional processor pins. This increases the overall flexibility of the system by allowing the limited number of controls pins on the processors to be used for other purposes.
IRR functionality:
The IRR captures the status of two external input devices that are connected to the Input Read pins (IRR0 and IRR1).
The contents of the IRR read from address x0000 from either port. During reads from the IRR, DQ0 and DQ1 are valid bits and DQ<15:2> are don?t care. Writes to address x0000 are not allowed from either port.
Address x0000 is not available for standard memory accesses when SFEN = VIL. When SFEN = VIH, address x0000 is available for memory accesses.
The inputs will be 1.8V/2.5V LVCMOS/3.0V LVTTL depending on the user?s supply voltage. The table below shows the IRR operation.
| /SFEN | /CE | R/W | /OE | /UB | /LB | ADDR | I/O0-I/O1 | I/O<15:2> | Mode |
| H | L | H | L | L | L | X000-Max | Valid | Valid | Standard Memory Access |
| L | L | H | L | X | L | X000 | Valid | X | IRR Read |
ODR functionality:
The ODR determines the state of up to five external binary state devices by providing a path to VSS for the external circuit. These outputs are Open Drain.
The five external devices can operate at different voltages (1.5V ≤ VDDIO ≤ 3.5V) but the combined current cannot exceed 40 mA (8 mA max for each external device). The status of the ODR bits are set using standard write accesses from either port to address x0001 with a ?1? corresponding to on and ?0? corresponding to off. The status of the ODR bits can be read with a standard read access to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for memory accesses.
When SFEN = VIH, the ODR is inactive and address x0001 can be used for standard accesses.
During reads and writes to ODR DQ<4:0> are valid and DQ<15:5> are don?t care. The table below shows the ODR operation.
| /SFEN | /CE | R/W | /OE | /UB | /LB | ADDR | I/O0-I/O4 | I/O<15:5> | Mode |
| H | L | H | X | L | L | X000-Max | Valid | Valid | Standard Memory Access |
| L | L | L | X | X | L | X001 | Valid | X | ODR Write |
| L | L | H | L | X | L | X0001 | Valid | X | ODR Read |
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