Explain SEL and SER for Cypress NVSRAM's
SEL (Single Event Latch-up) in nvSRAMs
Single Event Latch-up (SEL) is potentially destructive condition involving parasitic circuit elements forming a silicon controlled rectifier (SCR). Normally this SCR is off and only conducting leakage current. However, if enough voltage (called a threshold voltage) is put across the SCR by some parasitic event, the SCR turns on and conducts current. This current remains until the SCR is completely powered off, which is why this condition is called latch-up. In traditional SEL, the SCR device current may destroy the device if not current limited and removed in time. A removal of power to the device is required in all non-catastrophic SEL conditions in order to recover device operations. Several mitigation options used for standard latch-up issues can also be applied for SEL issues. The nvSRAM is well protected from SEL events by employing a triple well architecture underneath the memory core, which creates a low resistive Vcc collection layer for electrons, making it virtually impossible to accumulate enough isolated charge to create a voltage even approaching the threshold voltage required for latch-up.
Cypress has performed both alpha and neutron testing (the main cause of parasitic events in silicon) on our nvSRAMs to measure SEL. All tested samples of nvSRAM on S8 technology node successfully demonstrated Zero SEL events under extreme testing conditions.