PSoC® 3, PSoC 4 and PSoC 5 BSDL Files - KBA84780

Version: *B

 

Question:

What are JTAG BSDL files and where can I find them for PSoC 3, PSoC 4 and PSoC 5LP devices?

 

Answer:

 

BSDL files

 

The Boundary-Scan Description Language (BSDL) is a subset of VHDL (VHSIC Hardware Description Language) that describes how boundary-scan (JTAG) is implemented in a device and how the device operates. It defines the data transport characteristics of the device, i.e. how it captures, shifts, and updates scanned data. Boundary-scan tools usually require that the user supply BSDL files for the devices being used in order to properly generate test vectors and perform in-system programming and functional testing.

 

The BSDL file includes the following data:

 

  • Entity Declaration: Identifies the name of the device that is described by the BSDL file.
  • Generic Parameter: Specifies the package described.
  • Logical Port Description: Lists all the connections on the device. It defines its basic attributes, i.e., whether the connection is an input (in bit;), output (out bit;), bi-directional (inout bit;), buffer ( a 2-state output-only pin;),or if it is unavailable for boundaryscan (linkage bit;).
  • Package Pin Mapping: Used for determining the internal connections within the device. It details how the pads on the device die are wired to the external pins.
  • Use Statements: Calls the VHDL packages that contain the data that are referenced in the BSDL File.
  • Scan Port Identification: Identifies the particular pins that are used for the boundary-scan / JTAG implementation. These include: TDI, TDO, TMS, TCK and TRST (if used).
  • Test Access Port (TAP) Description: Provides additional information on the boundary-scan or JTAG logic for the device. The data includes the instruction register length, instruction opcodes, device IDCODE, etc.
  • Boundary Register Description: Provides the structure of the boundary-scan cells on the device. Each pin on a device may have up to three boundary-scan cells, each cell consisting of a register and a latch.

 

Location of BSDL Files

 

PSoC 4:

 

PSoC 4 does not support JTAG debug interface and thus boundary scanning cannot be done on it. The BSDL files thus, are not available for PSoC 4.

 

PSoC 3:

 

The BSDL files for PSoC 3 can be found in the root installation directory of PSoC Programmer –
C:\Program Files\Cypress\Programmer\3rd_Party_Configuration_Files\BSDL\PSoC3

 

You can download the latest release of PSoC Programmer from the following web page for the updated BSDL files - www.cypress.com/go/psocprogrammer

 

The BSDL files for every PSoC 3 part are also located at the end of the product part number page in the Technical Document Section as ‘Boundary Scan BSDL’.

 

There are four different BSDL files provided for every PSoC 3 package type based on the below classifications.

 

  • Operation Mode of USBIO pins: The USBIO pins on the PSoC 3 device can either be in USBIO mode or GPIO mode. Each of these modes has a separate BSDL file
  • JTAG configuration of the device: 4-wire JTAG and 5-wire JTAG are the two modes of JTAG operation in PSoC 3. The 4-wire JTAG does not support the nTRST JTAG pin while the 5-wire JTAG support nTRST JTAG pin. Devices coming from factory are configured in the 4-wire JTAG mode by default.

 

For Example: For PSoC 3 QFN-48 pin package, the files available are:
CY8C3XXXX_XXX_QFN48_4JTAG.bsdl -- (USB lines configured in GPIO mode and 4-wire JTAG mode)
CY8C3XXXX_XXX_QFN48_5JTAG.bsdl -- (USB lines configured in GPIO mode and 5-wire JTAG mode)
CY8C3XXXX_XXX_QFN48_USB_4JTAG.bsdl -- (USB lines configured in USBIO mode and 4-wire JTAG mode)
CY8C3XXXX_XXX_QFN48_USB_5JTAG.bsdl -- (USB lines configured in USBIO mode and 5-wire JTAG mode)

 

PSoC 5LP:

 

The BSDL files for PSoC 5LP can be found in the root installation directory of PSoC Programmer -
C:\Program Files\Cypress\Programmer\3rd_Party_Configuration_Files\BSDL\PSoC5LP

 

You can download the latest release of PSoC Programmer from the following web page for the updated BSDL files - www.cypress.com/go/psocprogrammer

 

The BSDL files for every PSoC 5LP part are also located at the end of the product part number page in the Technical Document Section as ‘Boundary Scan BSDL’.

 

PSoC 5LP has two Test Access Ports (‘TAP’ – JTAG Controller), one is the Test Controller TAP and the other is ARM Cortex M3 Debug Access Port TAP. The scan path in PSoC5LP is as follows:

 

PSoC 5LP

 

Capture_1.PNG

 

 

 

Similar to PSoC 3 we have four BSDL files for each TAP for PSoC 5LP, making 8 different BSDL files available with each package of PSoC 5LP. While running boundary scan on PSoC 5LP, you will need two BSDL files, one of each TAP to be provided to BoundaryScan Tools based on the configuration of the device.

 

There are four different BSDL files provided for every TAP of PSoC 5LP package type based on the below classifications.

 

  • Operation Mode of USBIO pins: The USBIO pins on the PSoC 5LP device can either be in USBIO mode or GPIO mode. Each of these modes has a separate BSDL file
  • JTAG configuration of the device: 4-wire JTAG and 5-wire JTAG are the two modes of JTAG operation in PSoC 5LP. The 4-wire JTAG does not support the nTRST JTAG pin while the 5-wire JTAG support nTRST JTAG pin. Devices coming from factory are configured in the 4-wire JTAG mode by default.

 

For Example: For PSoC 5LP QFN-68 pin package, the files available are:
For ARM Debug Access Port TAP:
CY8C58LPXXX_DAP_QFN68_4JTAG.bsdl -- (USB lines configured in GPIO mode and 4-wire JTAG mode)
CY8C58LPXXX_DAP_QFN68_5JTAG.bsdl -- (USB lines configured in GPIO mode and 5-wire JTAG mode)
CY8C58LPXXX_DAP_QFN68_USB_4JTAG.bsdl -- (USB lines configured in USBIO mode and 4-wire JTAG mode)
CY8C58LPXXX_DAP_QFN68_USB_5JTAG.bsdl -- (USB lines configured in USBIO mode and 5-wire JTAG mode)

 

For Test Controller TAP:
CY8C58LPXXX_QFN68_4JTAG.bsdl -- (USB lines configured in GPIO mode and 4-wire JTAG mode)
CY8C58LPXXX_QFN68_5JTAG.bsdl -- (USB lines configured in GPIO mode and 5-wire JTAG mode)
CY8C58LPXXX_QFN68_USB_4JTAG.bsdl -- (USB lines configured in USBIO mode and 4-wire JTAG mode)
CY8C58LPXXX_QFN68_USB_5JTAG.bsdl -- (USB lines configured in USBIO mode and 5-wire JTAG mode)

 

For the configuration of :
4 wire JTAG debug configuration, and USB IO in GPIO mode.
You will use two BSDL files: CY8C58LPXXX_DAP_QFN68_4JTAG.bsdl and CY8C58LPXXX_QFN68_4JTAG.bsdl., with the scan path as given in the above figure.