SLCS line of EZ-USB (FX1/FX2/FX2LP)

Version 1
    Question: Does SLCS# signal matter for Slave FIFO Sync Read and Slave FIFO Sync Write processes? If yes, what are the setup and hold time requirements to be met by an external IFCLK rising edge?



    The SLCS line is used only when external logic requires removing EZ-USB from the FIFO data bus for purposes like sharing the bus. The spec is setup time to IFCLK is 25 nsec and hold time from IFCLK is 10 nsec.