# DualPort: Using Extra Bits for Parity

Question: - Standard bus sizes are 8-bits, 16-bits, 32-bits or 64-bits.  Why are Cypress dual-ports offered in 9-bit, 18-bit, 36-bit, and 72-bit versions?  - What are the "extra" bits in the data bus used for?  - Are the extra bits parity bits?

A lot of the Cypress dual-ports have a slightly wider data bus than standard bus widths on processors.  These extra data bits are available to use at the customer's discretion.

Introduction to Parity

One possible use for the extra bits is for parity checking.  Parity is sometimes used as a simple way to test the validity of data.  There are two types of parity checking: even parity and odd parity.  For every 8 bits of data sent, an even parity generator will add the numbers in the 8-bit byte and generate a 0 if there are an even number of 1's, a 1 if there are an odd number of 1's.  An odd parity generator will be the opposite.  The original 8 bits of data are now "tagged" with an additional bit that indicates the parity of those bits.

These 9 bits are sent along the datapath to the destination.  The destination will have a parity checker which checks to make sure the tagged bit matches the actual data.  If the parity checker expects a "1" but sees a "0", then it will know that their must be some data corruption in the datapath.

How Cypress dual-ports support this protocol is by having an extra bit for every byte that can be used to pass the parity information along.  For example, if Processor A is connected to Processor B via a dual-port, and the system is using parity checking, then every byte from Processor A will be written into the dual-port along with a parity bit.  These 9-bits are stored in the dual-port memory until Processor B reads that address location.  Now, Processor B can verify that the parity bit matches the data.  See below for an example of how to connect a 32-bit processor with parity to the CY7C0852V 36-bit wide dual-port:

 Processor Signals Dual-port Signals DQ[0-7] I/O[0-7] Parity Bit #1 I/O[8] DQ[8-15] I/O[9-16] Parity Bit #2 I/O[17] DQ[16-23] I/O[18-25] Parity Bit #3 I/O[26] DQ[24-31] I/O[27-34] Parity Bit #4 I/O[35]

Design Considerations when Not Using Parity

When the native bus width is x16, x32, or x64, special considerations need to be taken when mapping those bits to the x18, x36, or x72 dual-ports to ensure that the byte enables are aligned correctly.  For example, if a 32-bit processor is connected to the CY7C0852V x36 dual-port, then the actual connections will have to be as shown below:

 Processor Signals Dual-port Signals DQ[0-7] I/O[0-7] I/O[8] = tied to GND/Vcc (unused) DQ[8-15] I/O[9-16] I/O[17] = tied to GND/Vcc (unused) DQ[16-23] I/O[18-25] I/O[26] = tied to GND/Vcc (unused) DQ[24-31] I/O[27-34] I/O[35] = tied to GND/Vcc (unused)