The PSoC 3 device family supports the IEEE 1149.1 JTAG interface for four or five pin configurations. The JTAG interface is used for programming the flash memory, debugging, I/O boundary scan, and JTAG device chaining.
The PSoC 3 programming algorithm does not support generalized JTAG programming languages such as SVF, STAPL, and others. This is due to specific timing requirements needed to program the PSoC 3 devices. To program the PSoC 3 devices using JTAG, a user must use MiniProg3 and PSoC Programmer or any other Cypress qualified programmers.
For Boundary Scan testing, PSoC 3 device will work with any standard JTAG Boundary scan development tool as long as the device is configured in JTAG 4 or 5 wire modes. All PSoC 3 devices which are coming out of factory are configured in JTAG 4 wire mode by default. So unless a user programs the device with SWD setting in .cydwr file of PSoC Creator™, PSoC 3 device supports Boundary scan by any standard tool.
As an additional note, PSoC 3 device programming through SWD is currently supported by a number of third party vendors listed on the general programming web page. We will continue to list the available SWD support and will add the JTAG support when available: