New clock synchronization check exposes aliased scan rate issue in CapSense

Question: Why does PSoC Creator 2.1 generate a clock synchronization warning in my working CapSense design?



PSoC Creator 2.1 adds a new timing design rule check (DRC) that is exposing a clocking problem in designs using the CapSense_CSD component. When the following conditions apply the actual scan rate is reduced due to aliasing with the synchronizing clock.


       BUS_CLK is not a multiple of 24MHz


       IMO is running at 24MHz


       CapSense_CSD component requests a 24MHz scan rate

The result of this situation is an actual scan rate of the difference between BUS_CLK and the IMO. Aside from not scanning at the expected rate there is no performance impact or failure risk because of this condition. Deployed CapSense designs built with PSoC Creator 1.0 and 2.0 will silently use the aliased clock speed but will not fail. The solution for new designs is to change the scan rate parameter in the component to a legal speed – either at BUS_CLK (if it is less than or equal to 24MHz) or at a frequency less than half of BUS_CLK. The easiest way to achieve this is to choose 12MHz or lower in the scan rate pull-down.



For more frequency choices the clock can be set to external (check the “Enable clock input” box) and any (legal) clock can be applied from the schematic, as follows.