Comparison of Resource Utilization Between PSoC® 3, PSoC 5 and PSoC 5LP UDBs and Other Vendor CPLDs - KBA85325

Question: How do PSoC UDBs compare with other vendor CPLDs for logic utilization of common functions?

 

Answer:

The table below compares the resource utilization of PSoC UDBs to that of CPLDs/FPGAs from vendors Altera, Lattice and Xilinx. The comparison is shown for I2C master and I2C slave for equivalent functional logic implementations. Composition of basic building blocks (for the devices) is explained after this table.

                                                                                                                             
   
    
     Module
    
  
   
     PSoC 3 /
     PSoC 5 /
     PSoC 5LP UDBs
    
  
   
     Altera:
     Device MAX V
     5M570ZM100C4
    
  
   
     Lattice:
     Device MACHXO2
     LCMXO2-256HCTQFP100
    
  
   
     Xilinx:
     Device CoolrunnerII
     XC2C384-7TQ144
    
  
    I2C Master   
     Macrocells: 33 of 192 (17.19%)
   
     Pterms: 98 of 384 (25.52%)
   
     Datapath cells: 2 of 24 (8.33%)
   
     Status Cells: 2 of 24 (8.33%)
   
     Control Cells: 1 of 24 (4.17%)
  
   
     Registers: 113 of 570 (20%)
   
     LUTs: 87 of 570 (32.8%)
   
     Logic elements: 199 of 570 (35%)
  
   
     Registers: 96 of 256 (37.5%)
   
     LUTs: 141 of 256 (55%)
   
     Slices: 72 of 128 (56%)
  
   
     Macrocells: 136 of 384 (36%)
   
     Pterms: 343 of 1344 (26%)
   
     Function blocks: 10 of 24 (41.5%)
  
   
     I2C Master blocks which can be fitted in the device: 3
  
   
     I2C Master blocks which can be fitted in the device: 3
  
   
     I2C Master blocks which can be fitted in the device: 2
  
   
     I2C Master blocks which can be fitted in the device: 2
  
    I2C Slave   
     Macrocells: 25 of 192 (13.02%)
   
     Pterms: 59 of 384 (15.36%)
   
     Datapath cells: 1 of 24 (4.17%)
   
     Status Cells: 1 of 24 (4.17%)
   
     Control Cells: 2 of 24 (8.33%)
  
   
     Registers: 73 of 570 (13%)
   
     LUTs: 114 of 570 (20%)
   
     Logic elements: 125 of 570 (22%)
  
   
     Registers: 72 of 256 (28%)
   
     LUTs: 100 of 256 (39%)
   
     Slices: 50 of 128 (39%)
  
   
     Macrocells: 79 of 384 (21%)
   
     Pterms: 196 of 1344 (22%)
   
     Function blocks: 6 of 24 (25%)
  
   
     I2C Slave blocks which can be fitted in the device: 4
  
   
     I2C Slave blocks which can be fitted in the device: 4
  
   
     I2C Slave blocks which can be fitted in the device: 3
  
   
     I2C Slave blocks which can be fitted in the device: 4
  

Architecture:

PSoC 3/PSoC 5/PSoC 5LP has total of 24 UDBs. Each UDB mainly consists of: 8 macrocells, PLA (which can implement 16 Product terms), 1 datapath cell, 1 Control cell and 1 Status cell.

Altera MAXV 570ZM device has a total of 570 Logic elements. Each logic element consists of: One 4-input LUT and One register (D flip-flop).

Lattice MACHXO2 256HC device has a total of 128 slices. Each slice consists of: Two 4-input LUTs and Two registers (D flip-flop).

Xilinx XC2C384 consists of 24 Function blocks. Each function block consists of 16 Macrocells and a PLA (which can implement 56 Pterms).

Conclusion:

Data from the above table shows that the PSoC 3/PSoC 5/PSoC 5LP UDB utilization is comparable to:

Mid to higher end CPLDs from Altera MAXV series

Mid to higher end CPLDs from Xilinx Cool runner series

Lower end to mid range FPGAs from Lattice’s MACHXO2 series