Question: What is the significance of the dummy read cycle in SynC SRAMs?
A dummy read cycle is used during the transition from a read cycle to a write cycle in order to avoid bus contention. During a read operation, the data lines will be driven by the SRAM. But for a write cycle, the data lines have to be tristated and the lines will be driven externally. If proper timings are met and data is given after the data line goes in to High Z state, the device will operate correctly. But if proper timings are not met, then a bus contention may occur. To be on the safe side, a dummy read cycle can be introduced between the read and write cycle. During the dummy read, the data lines will be in a high impedance condition. In the next cycle, give the data to be written.