Question: What are the rules for analog routing in PSoC 4 BLE?
Analog blocks in PSoC 4 BLE have the following high-level routing rules and possibilities. Figure 1 shows the routing diagram and the analog blocks in the chip.
Figure 1: Analog Routing in PSoC 4 BLE
PSoC 4 BLE has a Sequential SAR ADC block. The routing rules are as follows:
- SAR-ADC inputs can be routed to one of the following:
- External pins on Port 3
- AMUX-A / AMUX-B: these can be connected to multiple other blocks in the chip, including all port pins
- Opamp outputs (See the CTBm section)
- Temperature sensor
- The routing can be controlled via the SAR Sequencer, Firmware, or DSI (UDB)
- Routing inputs on Port 3:
- Single-ended channel inputs can be placed on any pin of Port 3
- In case of only one differential channel, the inputs can be placed on any pin of Port 3
- In case of multiple differential channels, the positive input must be on an even pin (0, 2, 4, 6), while the negative input must be on the consecutive odd pin (1, 3, 5, 7) of Port 3. Example, use P3.0/P3.1 for one channel and P3.4/P3.5 for the other channel.
This constraint is applicable when using the Sequencer to control routing. If this routing is not followed, the SAR Sequencer tries to use the AMUX to place the Component. In firmware-controlled or DSI-controlled routing, this constraint is not present.
- In case of multiple single-ended channels and one of them being on P3.4, the GPIO P2.4 cannot be routed to any of the AMUX buses.
- In case of multiple differential-ended channels and one of them being on P3.4/P3.5, the GPIOs P2.1 and P2.4 cannot be routed to any of the AMUX buses.
- If the channel input is on a port other than Port 3, AMUX-A/B buses are used to route the input to that pin. Here, two singleended channels or one differential channel can be used.
- If an external reference is used, the VREF pin of the chip is available, and no port pins can be used for the same.
PSoC 4 BLE has two CTBm blocks. Each CTBm has two Opamps (Opamp0 and Opamp1), the routing for which is detailed below:
- Positive terminal: For each Opamp, the positive terminal can connect to one of two fixed GPIOs, or one of the two AMUX buses.
For Opamp0, the input can connect to Pin 0 or Pin 6 of the corresponding port, or to AMUX-A.
For Opamp1, the input can connect to Pin 5 or Pin 7 of the corresponding port, or to AMUX-B.
- Negative terminal – For each Opamp, the negative terminal can connect either to a fixed GPIO, or to the output of the Opamp.
For Opamp0, the GPIO is Pin 1 of the corresponding port.
For Opamp1, the GPIO is Pin 4 of the corresponding port.
- Output terminal: The Opamp output terminal can connect either to a GPIO, or to the SAR-ADC through the SARBUS.
For Opamp0, the output can connect to Pin 2 of the corresponding port, or to SARBUS0.
For Opamp1, the output can connect to Pin 3 of the corresponding port, or to SARBUS0 or SARBUS1.
CTBm0 is associated with Port 2, while CTBm1 is associated with Port 1.
The CapSense block can connect to any GPIO via AMUX buses. Also, the IDAC blocks in CapSense can be connected to the AMUX bus, which can then connect to a GPIO or Opamp.
CapSense CMOD and CSH_TANK pins are connected to P4 and P4 respectively, and if any other pins have to be used for this purpose, then AMUX buses must be used to connect to those GPIOs.
There are two low-power comparators (LPCOMP0, LPCOMP1) in the chip. Their routing is as follows:
LPCOMP0 input terminals are P0 for positive and P0 for negative input
LPCOMP1 input terminals are P0 for positive and P0 for negative input.
LPCOMP output toggle (edge) can trigger an interrupt, which can be used to detect a signal change.
LPCOMP output can also be routed to a GPIO or other blocks of the chip via DSI.
For more details on the analog routing, refer to the PSoC 4 BLE Architecture TRM.