Reference Schematic Design and Layout Guidelines for Cypress’s Standard Sync/NoBL SRAMs - KBA203263

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Question:

Where can I get the reference schematic design and layout guide lines for Standard Sync/NoBL SRAMs?

 

Answer:

This knowledge base article provides the reference design schematic and layout guidelines for Cypress’s Standard Sync/NoBL SRAMs. Because Standard Sync/NoBL SRAMs operate at frequencies below 250 MHz, they can be interfaced directly with FPGA/ASIC applications. See the following schematic diagrams as a reference for designs with Cypress’s Standard Sync/NoBL SRAMs.

 

Reference Schematic for Standard Synchronous SRAMs

Reference Schematic for Standard Synchronous SRAMs.png

 

 

 

Reference Schematic for Synchronous NoBL SRAMs

 

Reference Schematic for Synchronous NoBL SRAMs.png

 

 

 

Even though the connections are straight-forward, we recommend that you to perform signal integrity simulations using IBIS models and add series or parallel termination resistances if required. Common types of terminations used are shown below:

 

Common types of terminations.png

 

 

 

Decoupling Capacitors

 

Values of decoupling capacitors for the power supply depend upon board and device properties. We recommend performing power integrity simulations before selecting decoupling capacitors. See the application note AN84060 to determine board decoupling capacitors.

 

Layout Guidelines for Standard Sync/NoBL SRAMs

 

Because Standard Sync/NoBL SRAMs operate at frequencies below 250 MHz, if you follow the following rules, they should work properly:

 

  • In Standard Sync/NoBL SRAMs, a single clock captures address, data, and control signals. Therefore, the length of the memory address, control, and data lines should be carefully matched with the clock signal line to achieve proper setup and hold times.
  • Each address and data group should be matched within the bus as well. Ideally, there should be zero skew between the signals within a signal group.
  • If possible, route the data, address, and control signal groups in such a way that they are on the same layer as the CLK within ±10 to ±20 ps skew (ideal case) with the CLK traces.
  • If the trace lengths of clock, address, data, and control signals do not match with each other, then FPGA/Processor should accommodate the propagation delay caused due to trace length differences. The FPGA/Processor should issue the signals in such a way that all signals reach the receiver side with the clock center-aligned with address, data, and control signals.