Configuring EZ-USB® FX3™ GPIF-II DLL - KBA210733

Version: **

 

Question:

What parameters should be used to configure the GPIF-II DLL block on the EZ-USB FX3 part?

 

Answer:

The GPIF-II block on the EZ-USB FX3 can function in various modes with different clock frequencies. The Delay Locked Loop (DLL) associated with GPIF-II is used to guarantee the timing parameters for the interface in certain operating modes. The main operating modes for GPIF-II can be classified into:

 

  1. No interface clock (Asynchronous mode)
  2. Interface clock driven by FX3 (Synchronous Master mode)
  3. Interface clock input to FX3 (Synchronous Slave mode)

 

In the two synchronous modes, the supported interface clock range is from 10 MHz to 100 MHz. In general, the DLL is not required to be turned ON when the FX3 is operating in a synchronous mode with an external clock input.

 

When the GPIF-II is configured in asynchronous mode or in synchronous master mode (PCLK is provided by FX3), the interface timing parameters are satisfied only if the DLL block associated with GPIF II is enabled.

 

The DLL configuration to be used in a specific application depends on factors such as the interface mode and the clock frequency used. The following sections describe the DLL features and the desired configuration for various interface modes.

 

1. GPIF-II DLL FEATURES

 

Some modes of the GPIF-II operation do not require the DLL. In such a case, the GPIF-II interface works on the basis of an internally generated clock, or an externally input PCLK.

 

The internal clock is generated from the FX3 SYSCLK which runs at a nominal frequency of 384 MHz using a programmable divider. The divisor used for the clock generation is specified through the CyU3PPibClock_t parameter passed to the CyU3PPibInit() API.

 

Internal PIB Clock Generation_0.png

Figure 1: Internal PIB Clock Generation

 

The DLL takes in the internal PIB clock and/or the external PCLK as inputs, and generates a set of three clocks:

 

  1. Core Clock: This is the clock used by the GPIF-II block to sample all input signals including the data bus.
  2. Output Clock: This is the clock used by the GPIF-II block to drive all output signals including the data bus.
  3. Sync/Master PIN Clock: In synchronous master mode, this is the actual source of the PCLK output from FX3. In asynchronous mode, this clock is used to synchronize the input signals on the interface. This clock is not used in synchronous slave mode.

 

GPIF-II DLL Block Diagram.png

Figure 2: GPIF-II DLL Block Diagram

 

These three clocks will all have the same frequency, but will have a programmable phase difference between them. The phase difference is achieved by selecting each of these clocks from among a set of 16 different phases of a single clock. The 16 phases supported will differ from each other by 360/16 = 22.5 degrees (differ by 1/16th of the clock period).

 

The timing parameters for the interface are achieved by selecting a set of relative phase differences that meet the requirements. The DLL can be operated in one of two possible modes:

 

1.1 Master Mode

 

When the DLL_MODE (bit 16) of the register is selected as MASTER (0), the DLL block generates the three clock outputs on the basis of the internal clock or the external PCLK. The delay to be applied is determined by the DLL based on feedback inputs.

 

1.2 Slave Mode

 

In the Slave Mode, the DLL functions as a programmable slave. The delay applied is determined by the value programmed into bits 26:17 of the DLL_CTRL register. When the DLL is being operated in this mode, it is not required that the DLL will achieve lock to the input clock.

 

Note: The DLL Master / Slave mode is not to be confused with the GPIF-II Master / Slave modes. Later sections of this document describe the complete DLL configuration to be used for various GPIF-II interfaces

 

The DLL configuration for both of these modes is done through the PIB_DLL_CTRL register. The fields in this register are shown in Table 1. Recommendations on how these register fields are to be programmed are provided in Section 2.

 

Table 1: PIB_DLL_CTRL Register Definition

                                                                                                                                                                                                                      

PIB_DLL_CTRL Register Address = 0xE0010028
Field NameBit RangeDescription
ENABLE0DLL Enable bit
    0: DLL is disabled
    1: DLL is enabled
HIGH_FREQ1Whether the PCLK frequency is high
    0: PCLK frequency < 70 MHz
    1: PCLK frequency ≥ 70 MHz
DLL_STAT2Whether DLL has achieved phase lock
    0: DLL has not achieved phase lock
    1: DLL has achieved phase lock
CORE_PHASE7:4Selects the core clock phase.
    Please follow recommendation in Table 2.
SYNC_PHASE11:8Selects the sync clock phase.
    Follow the recommendation in Table 2
OUTPUT_PHASE15:12Selects the output clock phase.
    Follow the recommendation in Table 2
DLL_MODE16DLL mode selection.
    0: DLL is in master mode and locks to the input clock
    1: DLL is in slave mode and creates delayed versions of input clock
SLAVE_DELAY26:17Delay to be applied to the input clock when operating in slave mode.
SLAVE_MODE29:27Additional slave mode configuration
    000: Master mode operation
    111: Slave mode operation
    Other values are reserved.
DLL_RESET_N30Reset control for the DLL.
    0: DLL is held in reset.
    1: DLL is not in reset

 

2. DLL CONFIGURATION

 

The DLL configuration to be used when the GPIF-II is used to implement various interfaces has been characterized for the FX3 device across various operating voltage and temperature conditions.

 

Table 2: DLL Configuration for Various Interfaces

                                                                                                                                                                                                                                                                                  

DLL ParameterDLL Parameter GPIF Interface Type
Synchronous Slave
    (Input PCLK)
Synchronous Master
    (Output PCLK ≥ 80 MHz)
Synchronous Master
    (Output PCLK < 80 MHz)
Asynchronous
    Master/Slave
DLL ENABLENoYesYesYes
HIGH_FREQDon’t care101
CORE_PHASEDon’t care000111110000
SYNC_PHASEDon’t care000011111000
OUTPUT_PHASEDon’t care101110110000
DLL_MODEDon’t careMaster (0)Slave (1)Master (0)
SLAVE_DELAYDon’t careDon’t care0x46Don’t care
SLAVE_MODEDon’t care000111000
Wait for DLL LockNoYesNoYes

 

Table 2 shows the DLL configuration that should be chosen when the GPIF-II is implementing various types of interfaces.

 

2.1 Configuring the DLL

 

The FX3 firmware library currently does not have any APIs which can fully configure the DLL. The DLL needs to be configured through direct writes to the PIB_DLL_CTRL register. The programming sequence to configure the DLL is shown below. 

 

  1. Configure the GPIF-II clock and power on the block using the CyU3PPibInit() API. The isDllEnable parameter to this function can be set to CyFalse, even if the DLL needs to be enabled. The DLL configuration and enabling will be done in the next step.
  2. If the DLL is required (not in synchronous slave mode), write to the PIB_DLL_CTRL register with the entire configuration as shown in Table 2. The DLL ENABLE bit can also be set in the same write operation.
  3. Reset the DLL by clearing the DLL_RESET_N bit, and apply a 1 µs delay.
  4. Bring the DLL out of reset by setting the DLL_RESET_N bit. 5. If the DLL should lock, wait for the DLL_STAT bit in the register to be set. 6. Proceed with the rest of the initialization including GPIF-II configuration loading.

 

If any changes are to be made to the DLL configuration at runtime, it is recommended that the entire GPIF-II block be powered down and reinitialized using the CyU3PPibDeinit() and CyU3PPibInit() APIs.