Question:

Is the BCH-24 ECC algorithm valid on Cypress S34ML02G2?

Answer:

The short answer is **“yes”**. See below for details and other considerations.

ECC protection is limited by the number of spare bytes available in a flash page, but it is also affected by the number of partial pages within the scope for the ECC. In the case of S34ML02G2, the spare area available per 2K page is 128 bytes. Here is the spare area size versus density for the members of the S34ML-2 family:

S34ML-2 Family Device | Spare Area Size (B) |

S34ML01G2 | 64 |

S34ML02G2 | 128 |

S34ML04G2 | 128 |

S34ML08G2 | 128 |

S34ML16G2 | 128 |

Using Tables 1-3 below, here is the number of parity bytes required if the BCH-24 ECC is applied to one, two, or four 512B partial pages:

Number of 512BPartial Pages, N | BCH-24 Parity Bytesper 2048B/N | Excess Bytes for64B/N Spare | Excess Bytes for128B/N Spare |

4 | 39 | -23 | -7 |

2 | 42 | -10 | 22 |

1 | 45 | 19 | 83 |

In the table, green numbers show the parity bytes that can fit with room to spare, while red numbers cannot fit. So for a 64B spare – i.e., for S34ML01G2 - the only way BCH-24 can work is if the ECC scope is 2KB. *However for 128B spare – like for S34ML02G2 - BCH-24 can work if the ECC scope is either 1024B or 2048B, but it cannot work if the ECC scope is 512B.*

Note also that the S34ML-2 family of NAND flash requires at least 4 bits of error correction per 512B partial page – although you may use more powerful correction if it is available. Now, looking at the minimal ECC case with 4 bits of correction per 512B page, 8 bits of correction per 1024B page, and 16 bits of correction per 2048B page:

Number of 512B Partial Pages, N | Bits of Correction per 2048B/N @ 4 bits per 512B | BCH Parity Bytes | Excess Bytes for 64B/N Spare | Excess Bytes for 128B/N Spare |

4 | BCH-4 | 7 | 9 | 25 |

2 | BCH-8 | 14 | 18 | 50 |

1 | BCH-16 | 30 | 34 | 98 |

The tables shown in attached file show the parity bits for ECC Correction bits from BCH-1 to BCH-40. The green shows the ECC parity byte counts that can fit in the 64B and 128 B spare, while red shows the ECC parity byte counts that can fit in the 128 B spare. Note that the BCH correction power applies to a “BCH Block Size” that is larger than the “main + spare” area quoted in the table heading. This means the BCH algorithm has enough excess correction power that not only can it correct for the main page scope, but it can also correct errors in any “extra” spare area bytes that are not occupied by ECC.

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