What is DMOS5 to DMOS6 conversion of 4 Kb/16 Kb/64 Kb F-RAM™ parts? Why do ESD values differ in the datasheets for new DMOS6 parts from the datasheets for the DMOS5 wafer parts? Does this ESD value difference impact my current applications?
DMOS5 to DMOS6 conversion of 4 Kb/16 Kb/64 Kb F-RAM parts
The 4 Kb/16 Kb/64 Kb serial (SPI and I2C) F-RAMs are a two-die solution:
- F-RAM core-die, which includes the F-RAM array and sense amplifier circuits
- Logic-die, which includes the serial interface logic, I/O controls, I/O pads, and regulator circuits
The migration from DMOS5 to DMOS6 is for the F-RAM core-die, while the logic-die remains identical to previous generation (DMOS5) parts. This migration is primarily to achieve the manufacturing of 4 Kb/16 Kb/64 Kb serial F-RAMs on an advanced 12-inch wafer facility without changing or optimizing any logic design or circuits. Therefore, the new DMOS6-based 4 Kb/16 Kb/64 Kb serial F-RAMs are form-factor and function-compatible to the existing DMOS5 parts.
4 Kb/16 Kb/64 Kb F-RAM parts:
I2C: FM24C04B, FM24CL04B, FM24C16B, FM24CL16B, FM24C64B, FM24CL64B
SPI: FM25040B, FM25L04B, FM25L16B, FM25C160B, FM25640B, FM25CL64B
ESD values in the new DMOS6 parts are different from previous generation DMOS5 wafer parts
Even though DMOS6 wafer devices are identical to DMOS5 wafer devices in all aspects, you may notice differences in their ESD values for Human Body Model (HBM), Charged Device Model (CDM), and removed Machine Model (MM) specifications.
The original 4 Kb/16 Kb/64 Kb serial F-RAMs on DMOS5 were built and qualified by Ramtron and integrated with Cypress after Ramtron’s acquisition in 2012. Migration from DMOS5 to DMOS6 is a fab transfer process by Cypress; therefore, all functionalities, parameters, and reliability specifications are requalified and revalidated to guarantee the DMOS6 part datasheet specifications. Cypress has performed component-level ESD tests on DMOS6 devices according to the JEDEC standard as follows:
- HBM (JEDEC JESD22-A114-B) – Classification level 2: 2000V to < 4000 V; Cypress datasheet guarantees minimum 2 kV.
- CDM (JEDEC JESD22-C101-A) – Classification level C2a (or 2a): 500 V to < 750 V; Cypress datasheet guarantees minimum 500 V.
The JEDEC standard for the component-level ESD classification for HBM and CDM are shown in Table 1 and Table 2 respectively. Cypress does not test MM because JEDEC has discontinued the MM ESD test. DMOS 6 devices are tested for much higher limits for both HBM and CDM than shown in the respective part datasheets. The actual tested ESD voltage limits are available in the Qualification Test Plan (QTP) document attached to the product pages on www.cypress.com.
Table 1. HBM ESD Component Classification Levels
|Classification||Voltage Range (V)|
|0B||125 to < 250|
|1A||250 to < 500|
|1B||500 to < 1000|
|1C||1000 to < 2000|
|2||2000 to < 4000|
|3A||4000 to < 8000|
Reference: JEDEC/ESDA HBM (JESD22-A114F)
Table 2. CDM ESD Component Classification Levels
|Classification||Voltage Range (V)|
|C0b||125 to < 250|
|C1||250 to < 500|
|C2a||500 to < 750|
|C2b||750 to < 1000|
Reference: JEDEC/ESDA CDM (JEDEC JESD22-C101F)
Impact of ESD value difference on current applications
DMOS5 to DMOS6 conversion is limited to the F-RAM core-die, which interfaces to the logic-die internally. None of its pads are bonded on any package pin in any form. All device pins in 4 Kb/16 Kb/64 Kb serial F-RAMs are bonded to the logic-die pads, which are unchanged in DMOS5 to DMOS6 conversion parts. Hence, the ESD protection circuits and their tolerance levels are identical between DMOS5 and DMOS6.
As Table 1 shows, ESD HBM classification 2 defines the voltage tolerance limit > 2000 V up to 4000 V (4000 V excluded). Therefore, all components qualified within this voltage range are ESD HBM Class 2 qualified.
Similarly, in Table 2, ESD CDM classification C2a (or 2a) defines the voltage tolerance limit of > 500 V up to 750 V (750 V excluded). Therefore, all components qualified for any value within this voltage range are ESD CDM Class 2a qualified.
Figure 1. CDM Qualification Roadmap
JEDEC provides a CDM qualification roadmap for various technology nodes, as shown in Figure 1. Because 4 Kb/16 Kb/64 Kb serial F-RAM devices are built on 130-nm technology node, a > 500 V CDM qualification falls within the JEDEC recommended limit for 130- nm technology.
To conclude, ESD (HBM and CDM) datasheet parameters for products built in DMOS6 provide identical ESD performance and meet the JEDEC standard. To learn more about the ESD test results, refer to the Qualification Test Plan (QTP) document attached to the product pages on www.cypress.com.
Reference: Industry Council - CDM Roadmap