What is the Chip Enable Don’t Care feature in NAND devices?
Early NAND devices required the NAND controller to assert Chip Enable (CE#) continuously throughout a Page Read or a Page Program command sequence. That means the controller must hold CE# low for multiple commands for entering instructions, addresses, and data. Typically, a memory controller would satisfy this requirement by implementing a latch glue logic to control the CE# signal, as well as the ALE and CLE signals.
Current NAND devices implement the “Chip Enable Don’t Care” feature. With this feature, the controller can de-assert CE# in between commands in the same command sequence. Also, the ALE and CLE signals are ignored if CE# is de-asserted. This approach allows the memory controller to eliminate the latch glue logic for lower cost in gates and less overhead in CPU cycles, and to allow code shadowing from NAND to RAM.
This feature is offered in all modern NAND devices. In Cypress NAND datasheets, this feature is illustrated by the shaded areas in the timing diagram as shown below (002-00499 Rev N). Within the times in shaded areas, the value of the CE# is “don’t care”.