PSoC 6 BLE Hardware Design Considerations (Draft) Part 4


We are currently drafting a PSoC 6 BLE Application Note (AN) on hardware design considerations. Placed here is part 4 of the AN, covering PSoC 6 BLE's  XRES, GPIOs, and Programming and Debugging pins. PSoC 6 BLE has a reset pin, XRES (active LOW), a program and debug interface that provides a communication gateway for an external device to perform programming or debugging, and flexible GPIO pins, which can be controlled by firmware or have alternative connections depending on the PSoC 6 BLE peripheral. This draft covers the hardware design considerations for XRES, GPIOs, and programming an debugging pins.


Feel free to leave comments and ask questions, we appreciate the feedback!