We are currently drafting an Application Note (AN) on PSoC 6 BLE and its interrupt system. Placed here is part 1 of this AN, covering PSoC 6 BLE interrupt architecture and interrupt execution flow. PSoC 6 BLE supports interrupts and exceptions on both the Cortex-M4 and Cortex-M0+ cores. Interrupts are events generated by peripherals external to the CPU, such as timers or port pin signals, and exceptions are events that are generated by the CPU such as memory access faults and internal system timer events. This draft provides explanations on the interrupt architecture, interrupt sources, interrupt and power modes, and interrupt execution flow.
Feel free to read through and leave your feedback or questions in the comments section. We appreciate the feedback!