Selection of Vref in PSoC 6 and PSoC 4 SAR ADC – KBA230026

Version 2

    Author: VasanthR_91            Version: **


    Translation - Japanese: PSoC 6およびPSoC 4 SAR ADCのVrefの選択 – KBA230026 - Community Translated (JA)


    Selecting the right Vref for SAR ADC will depend upon the application requirements. PSoC 6 SAR ADC architecture is very similar to the PSoC 4 family devices. Therefore, the following discussion is applicable for both PSoC 6 and PSoC 4 devices. The options available to the customer on selection of Vref are: System bandgap reference, VDDA, VDDA/2, and external Vref.




    System Bandgap

    Dedicated internal connection to the main 1.2-V reference

    External device pin

    Some PSoC 6 devices support a dedicated pin, which is used for the Vref off-chip bypass capacitor and for the injection of a reference external to the chip. Checking the Vref bypass option has no effect in this mode.

    If the selected PSoC 6 device does not support this dedicated pin, this reference option will not be visible.


    An internal resistor divider produces VDDA/2 as a reference


    This mode uses the internal analog supply voltage applied to the VDDA terminals. The off-chip bypass capacitor has no effect in this mode.


    The main parameters that influence the selection of SAR Vref are the range of input signal, resolution, and the rate of conversion.


    Range of input signal: Vref should be selected such that the input range of SAR ADC covers the range of the input; otherwise, ADC results will be saturated. Adding a resistive divider to reduce the voltage range at input also introduces errors into the result due to the individual divider resistor tolerances. Because PSoC SAR ADC is a differential design, selecting Vref involves other aspects as well. When this ADC is used in single-ended mode, there is an option to select the Vneg input terminal connection. It can be connected to either VSSA, external pin, or Vref. If Vref is selected, the complete signal range must be covered and the resolution of the ADC should be unaffected. Selecting VSSA for Vneg will halve the operating range of ADC because the GPIOs used for ADC inputs do not accept negative voltages. However, selecting a value VDDA/2 (internally or externally), will give full resolution on the complete range.


    Resolution: As specified in the previous case, the ADC configuration and selection of Vref affects the resolution of the ADC. Also, if the application requirement is high resolution, a low noise and precise reference should be selected. The internal bandgap reference has 1% tolerance. If the application needs closer tolerance, external reference can be used. VDDA/2 will also include the tolerance of the resistor divider used to generate it. The operating range of the device will also be under scrutiny.


    Rate of conversion: Higher rates of conversion introduces noise into the system. So, there are restrictions on the sample rate according to the reference selected. To overcome this issue, the voltage references are bypassed using an external capacitor. An external reference can also be used.