Calculation of Endurance Limit for FRAM Device – KBA229840

Version 2

    Author: PradiptaB_11           Version: *A

     

    Question: How is the endurance limit calculated for F-RAM devices?

     

    Answer: In this example, CY15E064Q part is considered for endurance limit calculation. The endurance mentioned in the device datasheet (CY15E064Q) is calculated in a different manner. See Table 1 for the endurance limit specified in the device datasheet.

     

    Table 1. Time to Reach Endurance Limit for Repeating 64-byte Loop

    SCK Freq

    (MHz)

    Endurance

    Cycles/sec

    Endurance

    Cycles/year

    Years to Reach Limit

    4

    7,480

    2.36 x 10

    42.3

    1

    1,870

    5.88 x 10

    170.1

     

    First let’s understand the internal architecture of FRAM. The FRAM in question is of 64 Kbit density. Internally it has 1K rows. Each row can store 64 bits of data or 8 bytes of data. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The endurance calculation, in the device datasheet, is for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop.

     

    The following are the given parameters the calculation:

    Opcode

    Address

    Data

    Total

    SCK Freq

    1 byte

    2-byte

    64 bytes

    67 bytes

    1 MHz

     

    Clock Frequency /Total number of bits = Endurance cycles/sec

    1 M / (67 * 8) = 1867 Endurance cycles/sec, approximated to 1870 Cycles/sec

     

    The WREN opcode sets the WEL bit, which is part of Status Register and not a part of main memory; hence not considered in the calculation.