Author: HPPC Version: **
How can the FPGA to FX3 interface be tested without connecting an image sensor for a FX3 + ECP5 FPGA based UVC camera design?
To test only the FPGA to FX3 interface, a color pattern with the required frame resolution size can be generated by FPGA and sent to FX3. A FPGA reference project that generates a color pattern is attached with this knowledge base article. The FPGA master will send a 1080p resolution video frame continuously to FX3 over the slave FIFO interface. You can use the FX3 firmware available with KBA229407 to test the attached FPGA project.
Figure 1. FX3 + ECP5 FPGA-based Camera Design
The FPGA design contains two modules. The first module generates a color pattern based on the frame resolution and the second module sends the received data to FX3, known as the FX3 Master FIFO interface. When the FIFO module stores one complete line in buffer 1, it sends out a signal to the FX3 Master FIFO interface to send the video data to FX3. Meanwhile, FPGA can store video data in FIFO buffer 2. Similarly, if FIFO buffer 2 has one full line, a notification is sent to the FX3 Master FIFO interface.
The color pattern will be similar to Figure 2 and will stream YUV format 1080p resolution at 60fps. Any standard UVC host application (such as e-CAMView) can be used to test the color pattern.
Figure 2. Color Pattern for UYVY 1920 x 1080 @60 fps Resolution
You can use the UART debug prints, to make sure that the frame rate and frame size match the streaming resolution. Figure 3 shows the debug prints when the 1080p UYVY resolution is streaming with 60fps. The number of DMA producer events, consumer events, last partial buffer size, complete frame size, and the frame rate are printed through UART.
Figure 3. Debug Prints with Frame Size and Frame Rate