How can I make a delay-line without using UDBs?
Many PSoC® 4 and PSoC 6 devices implement a Smart IO block. The Smart IO block includes eight LUTs and a data unit (DU). Each LUT can be configured as combinatorial or registered logic. The DU can implement many functions, such as counters, data matching, and shift register. The DU is supported in PSoC Creator™ 4.1 and later.
The following steps illustrate an example of an externally supplied 20-kHz square wave being delayed by a fixed amount of 8 usec:
1. Create a new project in PSoC Creator and place the source, Smart IO Components, and clock. Set the clock to 1.0 MHz.
2. Enable Smart IO. By default, Smart IO is not configured; inputs and outputs on the block are not displayed. When the Smart IO configuration screen opens, the General tab appears, by default. In this tab, connections and all parameters are blank. Change any one of the input fields of the DU to enable the configuration.
Now, the DU is highlighted indicating that it is in use, and the Data Unit tab is enabled.
3. Go to the Data Unit tab. The default logical block in schematic appears on the lower right.
4. Click the Opcode drop-down arrow, select Shift Right from the drop-down list, and click Apply. The Shift Right block appears on the lower right.
5. Set the length (size) of the shift register and click Apply.
6. Go to the General tab. Click the Clock drop-down arrow and select Divided clock (Active) from the drop-down list.
7. Select inputs to the Shift Right function:
Asynchronous load function must be set to 0. Set TR0 by selecting Constant 0 from the drop-down list.
Enable function must be set to 1. Set TR1 by selecting Constant 1 from the drop-down list.
Input data to the shift register. The input to TR2 should be the output from one of the LUTs. TR2 cannot be directly connected to a data input or GPIO.
8. Select a suitable LUT. In this example, select LUT0.
An error code indicates that the input is undefined
The input to LUT0 can be any of the data lines or half of the GPIOs. In this example, select gpio2 for each LUT0 Input. Then, click the connect bubble, on the lines, to set all three LUT0 inputs to gpio2. Here, you select GPIO2 because GPIO0 and GPIO1 are used for programming and debugging and are unavailable for Smart IO connection.
An error is displayed because the GPIO is not configured.
9. Set GPIO2 to Input(Async).
The shift register input connections are now configured.
10. In this example, LUT0 must now be programmed as a follower or buffer. Go to the LUT0 tab. Select Combinatorial from the Mode drop-down list.
Inputs 0, 1, and 2 are connected to the same source, GPIO0, so the Out encoding could follow any one of the inputs - 1, 1, 1 is convenient.
11. Route the DU output to a GPIO. The DU output does not connect directly to a GPIO, so it must be routed through another LUT. Each LUT output is connected to a single GPIO. GPIO0 and GPIO1 are used by debugging and programming pins and GPIO2 is already used as the input, and the next available pin is GPIO3. Select Output from the GPIO3 drop-down list.
An error is displayed for GPIO because GPIO3 is not yet routed.
12. Select LUT3, the only LUT that routes to GPIO3. The DU output connects only to Input 0 of each of the LUTs. Set LUT3 Input 0 to DU. LUT3 Input 1 and Input 2 must be connected. Since GPIO2 is already in use, it can be used for the connection.
13. Program LUT3 as a follower, but not in the same manner as LUT0. The DU connects only to Input0 of any of the LUTs, so the combinatorial logic must follow Input0.
Click OK. The General tab appears. Note that the Smart IO routing is complete.
14. Complete Smart IO connections. Click OK again. The schematic view returns. Adjust the position of the external pins to line with the GPIOs used. Adjust clock connection to utilize the same source as PWM. For this test example, set PWM period to 49 and compare with 24.
15. Generate the code. The source code is simple:
16. Build and program.
17. Test the shift register by providing an input and measure the output.
Connect Source_Out on P1.0 to SR_In on P0.2 (done here with a jumper wire on a dev kit):
Trace 1 is Source_Out -- SR_In
Trace 2 is SR_Out
The cursors indicate that the waveform is delayed by 8 usec.