Correlator to Demodulate FSK Signals using Smart I/O - KBA229212
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Version: *A
Translation - Japanese: スマートI / Oを使用してFSK信号を復調する相関器 - KBA229212 - Community Translated (JA)
Question:
How can I make a correlator to demodulate FSK signals?
Answer:
Frequency-shift keying (FSK) is commonly used as an encoding method in low-speed modems. The digital data is represented by two different frequencies. In this example, the high frequency (4.0 kHz) represents a logic '1;' the low frequency (2.0 kHz) represents a logic 0. The frequency is modulated at a rate of 1200 Baud.
The canonical means for detecting FSK data is the use of a correlator.
The correlator multiplies an input signal by a delayed copy of itself. The delay is selected so that at one frequency, the delay is a full cycle of one of the waveforms and half of the cycle of the other waveform. One cycle of 4.0 kHz is 250 µsec; one cycle of 2.0 kHz is 500 µsec. Thus, a delay of 250 µsec results in the right amount of time shift, 4.0 kHz by one cycle, 2.0 kHz by a half cycle. The delay is implemented with a shift register. The multiplier is implemented with an exclusive-OR gate (XOR) or exclusive_NOR.
During the delay, time output of the correlator is somewhat noisy. This is cleaned up with a low-pass filter and a hysteresis comparator to generate the demodulated digital data, an effort that is separate from the intent of this article.
The logic for the correlator is built completely within the Smart I/O; it requires separate clock to determine the delay. A step-by-step example will demonstrate the implementation of the correlator:
1. Place the Smart I/O, PWM, and clock.
2. Configure PWM clock to 24 MHz.
3. Add pins to the right of the Smart I/O for correlator in and out.
The Smart I/O is configured as a chain of shift registers, 8 bits from the data unit and 7 from the LUTs for a total of 15 bits. The last LUT in the chain is not registered and is used for the XOR.
4. Right-click Smart I/O to start configuration
5. Click the data3 drop-down and select Input (async).
6. Click the input drop-down and select TCPWM(5)line_compl.
This now displays the connections to the logic in the Smart I/O.
7. Step down the line of the shift register:
- Set all three inputs of LUT7 to gpio5.
- Set LUT0_Input0 to DU, set LUT0_Input1 and _Input2 to LUT1. DU has only one connection to LUT0; Input1 and Input2 must be tied to a 'dummy.'
- Set LUT1_Input2 to LUT0, set LUT1_Input0 and LUT1_Input1 to LUT2. LUT1_Input0 does not connect to LUT1, it must be tied to a 'dummy.'
- Set all three inputs of LUT2 to LUT1.
- Set all three inputs of LUT3 to LUT2.
- Set all three inputs of LUT5 to LUT3.
- Set all three inputs of LUT6 to LUT5.
- Set LUT4_Input0 to gpio5. This is the direct input to the XOR. Set LUT4_input1 and _Input 2 to LUT6. This is the shift register delayed input to the XOR.
- Select clock from the data3 drop-down.
8. Configure the Data Unit and the LUTs:
- Configure LUT7, LUT2, LUT3, LUT5, and LUT6 as D flip-flops.
- Go to the LUT7 tab.
- Select Out = 1 for Input0, Input1 and Input2 = 1, all others =0.
- Select Registered output from the Mode drop-down.
- Click Apply.
- Repeat for LUT2, LUT3, LUT5, and LUT6.
9. Configure LUT0 as D flip-flop:
- Go to the LUT0 tab.
Set Out to follow Input0 (from DU). Ignore other inputs. Select Registered output from the Mode drop-down.
10. Configure Data Unit:
- Go to the Data Unit tab.
- Select Shift Right from the Opcode drop-down.
- Enter 8 as the Size.
- Set DU_TR0 to 0 to enable Shift Right
- Set DU_TR1 to 1 to enable Shift Right
- Set DU_TR2 to LUT7
.
11. Configure LUT1 as D flip-flop:
- Go to the LUT1 tab.
- Set Out to follow Input2 (from LUT0). Ignore other inputs.
- Select Registered output from the Mode drop-down.
12. Configure LUT4 as XOR:
- Go to the LUT4 tab.
- Set Out to follow Exclusive-OR combination of Input0 (LUT5) and Input1 (LUT6). Input2 (LUT6) follows Input1 and is ignored.
- Select Combinatorial from the Mode drop-down. This output is not registered.
Smart I/O configuration is now complete.
13 Click Apply to show Smart I/O routing.
14. Click Hide routing matrix to simplify display of connections.
15. Click OK to return to schematic.
16. Configure PWM.
The period for the PWM is calculated by:
- Right-click PWM and click Configure.
- Click PWM.
- Set Period to 199 (Actual period is this number +1 count).
- Set Compare to 99 (Actual compare is this number +1 count).
- Retain the default values for remaining settings.
- Click OK to return to schematic view.
17. Connect pins:
- Route signal from PWM to Data3 on Smart I/O.
- Route gpio5 on Smart I/O to pin for Corr_In.
- Route gpio4 on Smart I/O to pin for Corr_Out. Pin assignments will be automatically made by PSoC® Creator™.
- Click the DWR pins view.
- Click Lock for each pin to display Port and Pin number for each signal on schematic.
18. Improve viewability of waveforms:
- Click Configure.
- Select Output from the gpio6 drop-down.
- Click OK to return to the schematic.
- Add Digital output pin to gpio6 and label as Delay.
19. Generate the code:
- Open the main.c file.
- Add the following code snippet:
TCPWM_1_Start();
SmartIO_1_Start();
while(1); - Build and program.
20. Test:
- Provide an external source of 1200 baud at 2.0 and 4.0 kHz. This can be done with a signal generator or a project on a separate PSoC device following the method mentioned in AN221886 - Using Smart I/O to Generate a Digital FSK Transmit Signal.
Trace 1: Modem data, 1200 baud Trace 2: Modulated FSK signal Trace 3: Delayed FSK signal Trace 4: Correlator Output Cursor shows edge to edge delay of approximately 250 µsec (within clock and sampling error) |
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Finer resolution on the delay and more exact correlation can be achieved by using a longer shift register and higher frequency clock, but 15 bits is the limit with a single Smart I/O. Cypress parts with multiple Smart I/O ports can be used if more accuracy is required