Improve the Phase Noise for CY29430/CY5107 when VCXO Is Enabled – KBA229132

Version 2

    Author: PradiptaB_11           Version: **


    Translation - Japanese: VCXOが有効な場合におけるCY29430 / CY5107の位相ノイズの改善– KBA229132- Community Translated (JA)


    Phase noise will be higher in VCXO mode when compared to the non-VCXO mode in general. CY29430 is a 16 pin QFN device from Cypress which has crystal oscillator inside, while the CY5107 is a wafer offered from Cypress which can be incorporated into different applications with any packaging.

    Do the following to improve phase noise when VCXO is enabled:


    1. Do not apply any external voltage (VC is the voltage at the VCXO pin) VC = VDD/2 when the device is configured to operate in VCXO mode. Setting the VC at VDD/2 may cause spurs at the output phase noise. Apply a voltage that is outside the range of VDD/2 – 10 mV to VDD/2 + 10 mV.
    2. For VCXO settings, add an LC filter circuit to ensure that a noise-free DC signal is applied at this input. The more the noise-free input, the less phase noise.
    3. Reduce the VCXO Bandwidth.


    See AN210253 for more information.